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https://github.com/projectacrn/acrn-hypervisor.git
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HV:Added implementation for PMI handler function
irq.c/.h: Added new variables(ctx_rflags, ctx_rip, ctx_cs) in irq_desc On each interrupt this information is populated Added api's to access the irq_desc members profiling.c: profiling_pmi_handler:On each PMI generates gets the context and other information that caused it Tracked-On: projectacrn#1409 Acked-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
This commit is contained in:
Chinthapally, Manisha
committed by
wenlingz
wenlingz
parent
a7cbee1802
commit
5985c1216e
@@ -13,7 +13,8 @@
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#define MAJOR_VERSION 1
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#define MINOR_VERSION 0
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#define LBR_NUM_REGISTERS 32U
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#define PERF_OVF_BIT_MASK 0xC0000070000000FULL
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#define LVT_PERFCTR_BIT_UNMASK 0xFFFEFFFFU
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#define LVT_PERFCTR_BIT_MASK 0x10000U
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#define VALID_DEBUGCTL_BIT_MASK 0x1801U
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@@ -24,6 +25,8 @@ static bool in_pmu_profiling;
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static uint32_t profiling_pmi_irq = IRQ_INVALID;
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extern struct irq_desc irq_desc_array[NR_IRQS];
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static void profiling_initialize_vmsw(void)
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{
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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@@ -324,9 +327,151 @@ static void profiling_handle_msrops(void)
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/*
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* Interrupt handler for performance monitoring interrupts
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*/
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static void profiling_pmi_handler(__unused unsigned int irq, __unused void *data)
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static void profiling_pmi_handler(unsigned int irq, __unused void *data)
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{
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/* to be implemented */
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uint64_t perf_ovf_status;
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uint32_t lvt_perf_ctr;
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uint32_t i;
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uint32_t group_id;
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struct profiling_msr_op *msrop = NULL;
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struct pmu_sample *psample = &(get_cpu_var(profiling_info.pmu_sample));
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struct sep_state *ss = &(get_cpu_var(profiling_info.sep_state));
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if ((ss == NULL) || (psample == NULL)) {
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dev_dbg(ACRN_ERR_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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return;
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}
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/* Stop all the counters first */
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msr_write(MSR_IA32_PERF_GLOBAL_CTRL, 0x0U);
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_entry_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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ss->total_pmi_count++;
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perf_ovf_status = msr_read(MSR_IA32_PERF_GLOBAL_STATUS);
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lvt_perf_ctr = (uint32_t)msr_read(MSR_IA32_EXT_APIC_LVT_PMI);
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if (perf_ovf_status == 0U) {
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goto reconfig;
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}
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if ((perf_ovf_status & 0x80000000000000FULL) == 0U) {
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ss->nofrozen_pmi++;
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}
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(void)memset(psample, 0U, sizeof(struct pmu_sample));
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/* Attribute PMI to guest context */
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if ((get_cpu_var(profiling_info.vm_info).vmexit_reason
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== VMX_EXIT_REASON_EXTERNAL_INTERRUPT) &&
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((uint64_t)get_cpu_var(profiling_info.vm_info).external_vector
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== VECTOR_PMI)) {
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psample->csample.os_id
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=(uint32_t) get_cpu_var(profiling_info.vm_info).guest_vm_id;
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(void)memset(psample->csample.task, 0U, 16);
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psample->csample.cpu_id = get_cpu_id();
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psample->csample.process_id = 0U;
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psample->csample.task_id = 0U;
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psample->csample.overflow_status = perf_ovf_status;
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psample->csample.rip = get_cpu_var(profiling_info.vm_info).guest_rip;
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psample->csample.rflags
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= (uint32_t)get_cpu_var(profiling_info.vm_info).guest_rflags;
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psample->csample.cs
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= (uint32_t)get_cpu_var(profiling_info.vm_info).guest_cs;
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get_cpu_var(profiling_info.vm_info).vmexit_reason = 0U;
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get_cpu_var(profiling_info.vm_info).external_vector = -1;
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/* Attribute PMI to hypervisor context */
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} else {
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psample->csample.os_id = 0xFFFFFFFFU;
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(void)memcpy_s(psample->csample.task, 16, "VMM\0", 4);
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psample->csample.cpu_id = get_cpu_id();
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psample->csample.process_id = 0U;
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psample->csample.task_id = 0U;
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psample->csample.overflow_status = perf_ovf_status;
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psample->csample.rip = irq_desc_array[irq].ctx_rip;
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psample->csample.rflags
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= (uint32_t)irq_desc_array[irq].ctx_rflags;
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psample->csample.cs = (uint32_t)irq_desc_array[irq].ctx_cs;
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}
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if ((sep_collection_switch &
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(1UL << (uint64_t)LBR_PMU_SAMPLING)) > 0UL) {
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psample->lsample.lbr_tos = msr_read(MSR_CORE_LASTBRANCH_TOS);
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for (i = 0U; i < LBR_NUM_REGISTERS; i++) {
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psample->lsample.lbr_from_ip[i]
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= msr_read(MSR_CORE_LASTBRANCH_0_FROM_IP + i);
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psample->lsample.lbr_to_ip[i]
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= msr_read(MSR_CORE_LASTBRANCH_0_TO_IP + i);
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}
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/* Generate core pmu sample and lbr data */
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(void)profiling_generate_data(COLLECT_PROFILE_DATA, LBR_PMU_SAMPLING);
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} else {
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/* Generate core pmu sample only */
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(void)profiling_generate_data(COLLECT_PROFILE_DATA, CORE_PMU_SAMPLING);
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}
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/* Clear PERF_GLOBAL_OVF_STATUS bits */
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msr_write(MSR_IA32_PERF_GLOBAL_OVF_CTRL,
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perf_ovf_status & PERF_OVF_BIT_MASK);
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ss->valid_pmi_count++;
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_exit_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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if (msrop->reg_type != (uint8_t)PMU_MSR_DATA) {
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if (msrop->msr_id != MSR_IA32_PERF_GLOBAL_CTRL) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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else {
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if (((perf_ovf_status >> msrop->param) & 0x1U) > 0U) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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}
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}
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reconfig:
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if (ss->pmu_state == PMU_RUNNING) {
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/* Unmask the interrupt */
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lvt_perf_ctr &= LVT_PERFCTR_BIT_UNMASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_start_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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} else {
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/* Mask the interrupt */
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lvt_perf_ctr |= LVT_PERFCTR_BIT_MASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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}
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}
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/*
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