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HV:Added implementation for PMI handler function
irq.c/.h: Added new variables(ctx_rflags, ctx_rip, ctx_cs) in irq_desc On each interrupt this information is populated Added api's to access the irq_desc members profiling.c: profiling_pmi_handler:On each PMI generates gets the context and other information that caused it Tracked-On: projectacrn#1409 Acked-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
This commit is contained in:
Chinthapally, Manisha
wenlingz
parent
a7cbee1802
commit
5985c1216e
@ -12,7 +12,7 @@ static spinlock_t irq_alloc_spinlock = { .head = 0U, .tail = 0U, };
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#define IRQ_ALLOC_BITMAP_SIZE INT_DIV_ROUNDUP(NR_IRQS, 64U)
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static uint64_t irq_alloc_bitmap[IRQ_ALLOC_BITMAP_SIZE];
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static struct irq_desc irq_desc_array[NR_IRQS];
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struct irq_desc irq_desc_array[NR_IRQS];
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static uint32_t vector_to_irq[NR_MAX_VECTOR + 1];
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spurious_handler_t spurious_handler;
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@ -350,7 +350,12 @@ void dispatch_interrupt(const struct intr_excp_ctx *ctx)
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/* mask irq if possible */
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goto ERR;
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}
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#ifdef PROFILING_ON
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/* Saves ctx info into irq_desc */
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desc->ctx_rip = ctx->rip;
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desc->ctx_rflags = ctx->rflags;
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desc->ctx_cs = ctx->cs;
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#endif
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handle_irq(desc);
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return;
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ERR:
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@ -372,6 +372,9 @@ int external_interrupt_vmexit_handler(struct vcpu *vcpu)
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}
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ctx.vector = intr_info & 0xFFU;
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ctx.rip = vcpu_get_rip(vcpu);
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ctx.rflags = vcpu_get_rflags(vcpu);
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ctx.cs = exec_vmread32(VMX_GUEST_CS_SEL);
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#ifdef CONFIG_PARTITION_MODE
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partition_mode_dispatch_interrupt(&ctx);
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@ -13,7 +13,8 @@
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#define MAJOR_VERSION 1
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#define MINOR_VERSION 0
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#define LBR_NUM_REGISTERS 32U
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#define PERF_OVF_BIT_MASK 0xC0000070000000FULL
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#define LVT_PERFCTR_BIT_UNMASK 0xFFFEFFFFU
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#define LVT_PERFCTR_BIT_MASK 0x10000U
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#define VALID_DEBUGCTL_BIT_MASK 0x1801U
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@ -24,6 +25,8 @@ static bool in_pmu_profiling;
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static uint32_t profiling_pmi_irq = IRQ_INVALID;
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extern struct irq_desc irq_desc_array[NR_IRQS];
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static void profiling_initialize_vmsw(void)
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{
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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@ -324,9 +327,151 @@ static void profiling_handle_msrops(void)
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/*
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* Interrupt handler for performance monitoring interrupts
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*/
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static void profiling_pmi_handler(__unused unsigned int irq, __unused void *data)
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static void profiling_pmi_handler(unsigned int irq, __unused void *data)
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{
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/* to be implemented */
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uint64_t perf_ovf_status;
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uint32_t lvt_perf_ctr;
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uint32_t i;
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uint32_t group_id;
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struct profiling_msr_op *msrop = NULL;
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struct pmu_sample *psample = &(get_cpu_var(profiling_info.pmu_sample));
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struct sep_state *ss = &(get_cpu_var(profiling_info.sep_state));
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if ((ss == NULL) || (psample == NULL)) {
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dev_dbg(ACRN_ERR_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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return;
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}
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/* Stop all the counters first */
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msr_write(MSR_IA32_PERF_GLOBAL_CTRL, 0x0U);
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_entry_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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ss->total_pmi_count++;
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perf_ovf_status = msr_read(MSR_IA32_PERF_GLOBAL_STATUS);
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lvt_perf_ctr = (uint32_t)msr_read(MSR_IA32_EXT_APIC_LVT_PMI);
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if (perf_ovf_status == 0U) {
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goto reconfig;
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}
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if ((perf_ovf_status & 0x80000000000000FULL) == 0U) {
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ss->nofrozen_pmi++;
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}
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(void)memset(psample, 0U, sizeof(struct pmu_sample));
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/* Attribute PMI to guest context */
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if ((get_cpu_var(profiling_info.vm_info).vmexit_reason
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== VMX_EXIT_REASON_EXTERNAL_INTERRUPT) &&
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((uint64_t)get_cpu_var(profiling_info.vm_info).external_vector
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== VECTOR_PMI)) {
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psample->csample.os_id
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=(uint32_t) get_cpu_var(profiling_info.vm_info).guest_vm_id;
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(void)memset(psample->csample.task, 0U, 16);
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psample->csample.cpu_id = get_cpu_id();
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psample->csample.process_id = 0U;
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psample->csample.task_id = 0U;
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psample->csample.overflow_status = perf_ovf_status;
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psample->csample.rip = get_cpu_var(profiling_info.vm_info).guest_rip;
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psample->csample.rflags
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= (uint32_t)get_cpu_var(profiling_info.vm_info).guest_rflags;
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psample->csample.cs
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= (uint32_t)get_cpu_var(profiling_info.vm_info).guest_cs;
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get_cpu_var(profiling_info.vm_info).vmexit_reason = 0U;
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get_cpu_var(profiling_info.vm_info).external_vector = -1;
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/* Attribute PMI to hypervisor context */
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} else {
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psample->csample.os_id = 0xFFFFFFFFU;
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(void)memcpy_s(psample->csample.task, 16, "VMM\0", 4);
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psample->csample.cpu_id = get_cpu_id();
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psample->csample.process_id = 0U;
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psample->csample.task_id = 0U;
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psample->csample.overflow_status = perf_ovf_status;
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psample->csample.rip = irq_desc_array[irq].ctx_rip;
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psample->csample.rflags
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= (uint32_t)irq_desc_array[irq].ctx_rflags;
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psample->csample.cs = (uint32_t)irq_desc_array[irq].ctx_cs;
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}
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if ((sep_collection_switch &
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(1UL << (uint64_t)LBR_PMU_SAMPLING)) > 0UL) {
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psample->lsample.lbr_tos = msr_read(MSR_CORE_LASTBRANCH_TOS);
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for (i = 0U; i < LBR_NUM_REGISTERS; i++) {
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psample->lsample.lbr_from_ip[i]
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= msr_read(MSR_CORE_LASTBRANCH_0_FROM_IP + i);
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psample->lsample.lbr_to_ip[i]
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= msr_read(MSR_CORE_LASTBRANCH_0_TO_IP + i);
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}
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/* Generate core pmu sample and lbr data */
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(void)profiling_generate_data(COLLECT_PROFILE_DATA, LBR_PMU_SAMPLING);
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} else {
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/* Generate core pmu sample only */
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(void)profiling_generate_data(COLLECT_PROFILE_DATA, CORE_PMU_SAMPLING);
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}
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/* Clear PERF_GLOBAL_OVF_STATUS bits */
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msr_write(MSR_IA32_PERF_GLOBAL_OVF_CTRL,
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perf_ovf_status & PERF_OVF_BIT_MASK);
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ss->valid_pmi_count++;
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_exit_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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if (msrop->reg_type != (uint8_t)PMU_MSR_DATA) {
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if (msrop->msr_id != MSR_IA32_PERF_GLOBAL_CTRL) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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else {
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if (((perf_ovf_status >> msrop->param) & 0x1U) > 0U) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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}
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}
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reconfig:
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if (ss->pmu_state == PMU_RUNNING) {
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/* Unmask the interrupt */
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lvt_perf_ctr &= LVT_PERFCTR_BIT_UNMASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_start_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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}
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}
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}
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} else {
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/* Mask the interrupt */
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lvt_perf_ctr |= LVT_PERFCTR_BIT_MASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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}
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}
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/*
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@ -488,6 +488,16 @@
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#define MSR_ATOM_LER_TO_LIP 0x000001DEU
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/* Last exception record to linear IP */
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#ifdef PROFILING_ON
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/* Core (and Goldmont) specific MSRs */
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#define MSR_CORE_LASTBRANCH_TOS 0x000001C9U
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/* Last branch record stack TOS */
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#define MSR_CORE_LASTBRANCH_0_FROM_IP 0x00000680U
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/* Last branch record 0 from IP */
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#define MSR_CORE_LASTBRANCH_0_TO_IP 0x000006C0U
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/* Last branch record 0 to IP */
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#endif
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/* LINCROFT specific MSRs */
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#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0U /* Configure CAR */
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@ -24,6 +24,11 @@ struct irq_desc {
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uint32_t flags; /* flags for trigger mode/ptdev */
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spinlock_t lock;
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#ifdef PROFILING_ON
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uint64_t ctx_rip;
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uint64_t ctx_rflags;
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uint64_t ctx_cs;
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#endif
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};
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int32_t request_irq(uint32_t req_irq, irq_action_t action_fn, void *priv_data,
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@ -33,6 +33,11 @@ enum MSR_CMD_TYPE {
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MSR_OP_READ_CLEAR
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};
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enum PMU_MSR_TYPE {
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PMU_MSR_CCCR = 0,
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PMU_MSR_ESCR,
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PMU_MSR_DATA
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};
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typedef enum IPI_COMMANDS {
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IPI_MSR_OP = 0,
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IPI_PMU_CONFIG,
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@ -212,6 +217,46 @@ struct sep_state {
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uint64_t saved_debugctl_value;
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} __aligned(8);
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struct core_pmu_sample {
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/* context where PMI is triggered */
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uint32_t os_id;
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/* the task id */
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uint32_t task_id;
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/* instruction pointer */
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uint64_t rip;
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/* the task name */
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char task[16];
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/* physical cpu ID */
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uint32_t cpu_id;
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/* the process id */
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uint32_t process_id;
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/* perf global status msr value (for overflow status) */
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uint64_t overflow_status;
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/* rflags */
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uint32_t rflags;
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/* code segment */
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uint32_t cs;
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} __aligned(SEP_BUF_ENTRY_SIZE);
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#define NUM_LBR_ENTRY 32
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struct lbr_pmu_sample {
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/* LBR TOS */
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uint64_t lbr_tos;
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/* LBR FROM IP */
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uint64_t lbr_from_ip[NUM_LBR_ENTRY];
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/* LBR TO IP */
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uint64_t lbr_to_ip[NUM_LBR_ENTRY];
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/* LBR info */
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uint64_t lbr_info[NUM_LBR_ENTRY];
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} __aligned(SEP_BUF_ENTRY_SIZE);
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struct pmu_sample {
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/* core pmu sample */
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struct core_pmu_sample csample;
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/* lbr pmu sample */
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struct lbr_pmu_sample lsample;
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} __aligned(SEP_BUF_ENTRY_SIZE);
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struct vm_switch_trace {
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uint64_t vm_enter_tsc;
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@ -228,6 +273,7 @@ struct profiling_info_wrapper {
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struct sep_state sep_state;
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struct guest_vm_info vm_info;
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ipi_commands ipi_cmd;
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struct pmu_sample pmu_sample;
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struct vm_switch_trace vm_switch_trace;
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socwatch_state soc_state;
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struct sw_msr_op_info sw_msr_op_info;
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