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Fix: write xmm registers correctly

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The movdqu instruction moves unaligned double quadword (128 bit)
contained in XMM registers.

This patch uses pointers as input parameters of the function
write_xmm_0_2() to get 128-bit value from 64-bit array for each XMM
register.

Tracked-On: #7380
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Jiang, Yanting <yanting.jiang@intel.com>
This commit is contained in:
Jiang, Yanting
2022-04-28 14:50:50 +08:00
committed by acrnsi-robot
parent 1540d3479f
commit 599894e571
2 changed files with 11 additions and 11 deletions
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16
hypervisor/include/arch/x86/asm/cpu.h Normal file → Executable file
View File

@@ -482,16 +482,16 @@ void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
: "r"(value)); \
}
#define CPU_XMM_READ(xmm, result_ptr) \
#define CPU_XMM_READ(xmm, result_m128i_p) \
{ \
asm volatile ("movdqu %%" STRINGIFY(xmm) ", %0": "=m" (*(result_ptr))); \
asm volatile ("movdqu %%" STRINGIFY(xmm) ", %0": "=m" (*(result_m128i_p))); \
}
#define CPU_XMM_WRITE(xmm, value) \
#define CPU_XMM_WRITE(xmm, input_m128i_p) \
{ \
asm volatile ("movdqu %0, %%" STRINGIFY(xmm) \
: /* No output */ \
: "m"(value)); \
: "m"(*(input_m128i_p))); \
}
static inline uint64_t sgdt(void)
@@ -749,11 +749,11 @@ static inline void read_xmm_0_2(uint64_t *xmm0_addr, uint64_t *xmm1_addr, uint64
CPU_XMM_READ(xmm2, xmm2_addr);
}
static inline void write_xmm_0_2(uint64_t xmm0_val, uint64_t xmm1_val, uint64_t xmm2_val)
static inline void write_xmm_0_2(uint64_t *xmm0_addr, uint64_t *xmm1_addr, uint64_t *xmm2_addr)
{
CPU_XMM_WRITE(xmm0, xmm0_val);
CPU_XMM_WRITE(xmm1, xmm1_val);
CPU_XMM_WRITE(xmm2, xmm2_val);
CPU_XMM_WRITE(xmm0, xmm0_addr);
CPU_XMM_WRITE(xmm1, xmm1_addr);
CPU_XMM_WRITE(xmm2, xmm2_addr);
}
/*