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remove check_tsc

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there is no need to clear CR4.TSD as there is no user mode
in ACRN hypervisor.

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ 2018-12-14 13:34:42 +08:00 committed by wenlingz
parent d2bac7cc5d
commit 59e3f562b8
4 changed files with 0 additions and 20 deletions
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3
doc/developer-guides/hld/hv-timer.rst
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@ -42,9 +42,6 @@ Interfaces Design
.. doxygenfunction:: timer_init
:project: Project ACRN
.. doxygenfunction:: check_tsc
:project: Project ACRN
.. doxygenfunction:: calibrate_tsc
:project: Project ACRN

3
hypervisor/arch/x86/cpu.c
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@ -429,9 +429,6 @@ void init_cpu_post(uint16_t pcpu_id)
enable_smap();
/* Make sure rdtsc is enabled */
check_tsc();
cpu_xsave_init();
if (pcpu_id == BOOT_CPU_ID) {

9
hypervisor/arch/x86/timer.c
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@ -189,15 +189,6 @@ void timer_init(void)
}
}
void check_tsc(void)
{
uint64_t temp64;
/* Ensure time-stamp timer is turned on for each CPU */
CPU_CR_READ(cr4, &temp64);
CPU_CR_WRITE(cr4, (temp64 & ~CR4_TSD));
}
static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
{
#define PIT_TICK_RATE 1193182U

5
hypervisor/include/arch/x86/timer.h
View File

@ -116,11 +116,6 @@ void del_timer(struct hv_timer *timer);
*/
void timer_init(void);
/**
* @brief Check tsc to make sure rdtsc is enabled.
*/
void check_tsc(void);
/**
* @brief Calibrate tsc.
*