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hv: trap vm0 write/read pm1a/pm1b registers

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ACRN needs to trap the pm1a/pm1b written/read from VM0. So we
could know when should we put the system to S3.

We will have two path back to VM0:
 - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec
   with real mode
 - S3 enter/exit failed. Will return to the next instruction of
   pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt
   register to check whether it's waked up or not.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yin Fengwei
2018-06-14 22:25:40 +08:00
committed by Xie, nanlin
parent baacfdbce9
commit 5b43521461
5 changed files with 109 additions and 1 deletions
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1
hypervisor/include/arch/x86/guest/guest_pm.h
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@@ -11,5 +11,6 @@ void vm_setup_cpu_state(struct vm *vm);
int vm_load_pm_s_state(struct vm *vm);
int validate_pstate(struct vm *vm, uint64_t perf_ctl);
struct cpu_cx_data* get_target_cx(struct vm *vm, uint8_t cn);
void register_pm1ab_handler(struct vm *vm);
#endif /* PM_H */

4
hypervisor/include/arch/x86/host_pm.h
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@@ -5,8 +5,12 @@
#ifndef HOST_PM_H
#define BIT_SLP_TYPx 10U
#define BIT_SLP_EN 13U
#define BIT_WAK_STS 15U
extern uint8_t host_enter_s3_success;
int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val);
extern void __enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,