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doc: Style cleanup in timer hld

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- Minor style changes per Acrolinx recommendations and for consistency

Signed-off-by: Reyes, Amy <amy.reyes@intel.com>
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Reyes, Amy 2022-02-28 12:09:46 -08:00 committed by David Kinder
parent 0283202193
commit 5c52f6fc2c
1 changed files with 3 additions and 3 deletions
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6
doc/developer-guides/hld/hv-timer.rst
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@ -6,7 +6,7 @@ Timer
Because ACRN is a flexible, lightweight reference hypervisor, we provide Because ACRN is a flexible, lightweight reference hypervisor, we provide
limited timer management services: limited timer management services:
- Only the lapic tsc-deadline timer is supported as the clock source. - Only the LAPIC tsc-deadline timer is supported as the clock source.
- A timer can only be added on the logical CPU for a process or thread. Timer - A timer can only be added on the logical CPU for a process or thread. Timer
scheduling or timer migrating is not supported. scheduling or timer migrating is not supported.
@ -14,11 +14,11 @@ limited timer management services:
How It Works How It Works
************ ************
When the system boots, we check that the hardware supports lapic When the system boots, we check that the hardware supports the LAPIC
tsc-deadline timer by checking CPUID.01H:ECX.TSC_Deadline[bit 24]. If tsc-deadline timer by checking CPUID.01H:ECX.TSC_Deadline[bit 24]. If
support is missing, we output an error message and panic the hypervisor. support is missing, we output an error message and panic the hypervisor.
If supported, we register the timer interrupt callback that raises a If supported, we register the timer interrupt callback that raises a
timer softirq on each logical CPU and sets the lapic timer mode to timer softirq on each logical CPU and sets the LAPIC timer mode to
tsc-deadline timer mode by writing the local APIC LVT register. tsc-deadline timer mode by writing the local APIC LVT register.
Data Structures and APIs Data Structures and APIs