hv: vlapic: clear up where needs atomic operation in vLAPIC

In almost case, vLAPIC will only be accessed by the related vCPU. There's no
synchronization issue in this case. However, other vCPUs could deliver interrupts
to the current vCPU, in this case, the IRR (for APICv base situation) or PIR
(for APICv advanced situation) and TMR for both cases could be accessed by more
than one vCPUS simultaneously. So operations on IRR or PIR should be atomical
and visible to other vCPUs immediately. In another case, vLAPIC could be accessed
by another vCPU when create vCPU or reset vCPU which could be supposed to be
consequently.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>

hypervisor/include/arch/x86/guest/vlapic.h

@@ -64,6 +64,8 @@ struct acrn_vlapic {
 	 * to support APICv features:
 	 * - 'apic_page' MUST be 4KB aligned.
 	 * - 'pir_desc' MUST be 64 bytes aligned.
+	 * IRR, TMR and PIR could be accessed by other vCPUs when deliver
+	 * an interrupt to vLAPIC.
 	 */
 	struct lapic_regs	apic_page;
 	struct vlapic_pir_desc	pir_desc;