From 5d6ce37bea605f88b8f8501cc1ce6ad61b87228b Mon Sep 17 00:00:00 2001 From: Victor Sun Date: Fri, 8 Jun 2018 12:26:18 +0800 Subject: [PATCH] HV: add Px Cx support for A3950 SoC Intel Atom A3950 SoC also can be used in Acrn, and it has same Cx data as Atom A3960 SoC. Signed-off-by: Victor Sun Reviewed-by: Kevin Tian --- hypervisor/arch/x86/cpu_state_tbl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hypervisor/arch/x86/cpu_state_tbl.c b/hypervisor/arch/x86/cpu_state_tbl.c index 8290584b5..f60c7a26e 100644 --- a/hypervisor/arch/x86/cpu_state_tbl.c +++ b/hypervisor/arch/x86/cpu_state_tbl.c @@ -34,6 +34,23 @@ struct cpu_cx_data cx_a3960[] = { {{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */ }; +/* The table includes cpu px info of Intel A3950 SoC */ +struct cpu_px_data px_a3950[] = { + {0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */ + {0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */ + {0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */ + {0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */ + {0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */ + {0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */ + {0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */ + {0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */ + {0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */ + {0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */ + {0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */ + {0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */ + {0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */ +}; + /* The table includes cpu px info of Intel J3455 SoC */ struct cpu_px_data px_j3455[] = { {0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */ @@ -62,6 +79,10 @@ struct cpu_state_table { {ARRAY_SIZE(px_a3960), px_a3960, ARRAY_SIZE(cx_a3960), cx_a3960} }, + {"Intel(R) Atom(TM) Processor A3950 @ 1.60GHz", + {ARRAY_SIZE(px_a3950), px_a3950, + ARRAY_SIZE(cx_a3960), cx_a3960} /* Cx is same as A3960 */ + }, {"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz", {ARRAY_SIZE(px_j3455), px_j3455, ARRAY_SIZE(cx_j3455), cx_j3455}