From 604b5a454b13e29c68bce829805763e4ce5ad97d Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Wed, 15 Aug 2018 01:13:21 +0000 Subject: [PATCH] hv: apicv: remove APIC_OFFSET_SELF_IPI(0x3F0) register From SDM Vol3 Table 10-1 Local APIC Register Address Map. The 0x3F0 is reserved. Signed-off-by: Yu Wang Acked-by: Anthony Xu --- hypervisor/arch/x86/guest/vlapic.c | 9 --------- hypervisor/arch/x86/guest/vlapic_priv.h | 1 - 2 files changed, 10 deletions(-) diff --git a/hypervisor/arch/x86/guest/vlapic.c b/hypervisor/arch/x86/guest/vlapic.c index 420cbc1dd..e5762e366 100644 --- a/hypervisor/arch/x86/guest/vlapic.c +++ b/hypervisor/arch/x86/guest/vlapic.c @@ -1431,12 +1431,6 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg, case APIC_OFFSET_TIMER_DCR: *data = lapic->dcr_timer; break; - case APIC_OFFSET_SELF_IPI: - /* - * XXX generate a GP fault if vlapic is in x2apic mode - */ - *data = 0UL; - break; case APIC_OFFSET_RRR: default: *data = 0UL; @@ -1527,9 +1521,6 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset, vlapic_esr_write_handler(vlapic); break; - case APIC_OFFSET_SELF_IPI: - break; - case APIC_OFFSET_VER: case APIC_OFFSET_APR: case APIC_OFFSET_PPR: diff --git a/hypervisor/arch/x86/guest/vlapic_priv.h b/hypervisor/arch/x86/guest/vlapic_priv.h index 0e0be0980..1388c4a66 100644 --- a/hypervisor/arch/x86/guest/vlapic_priv.h +++ b/hypervisor/arch/x86/guest/vlapic_priv.h @@ -80,7 +80,6 @@ #define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */ #define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */ #define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */ -#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI register */ /* * 16 priority levels with at most one vector injected per level.