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hv:Rename port/mmio read and write APIs

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mmio_write_long --> mmio_write32
mmio_write_word --> mmio_write16
mmio_write_byte --> mmio_write8
mmio_read_long  --> mmio_read32
mmio_read_word  --> mmio_read16
mmio_read_byte  --> mmio_read8

io_write_long --> pio_write32
io_write_word --> pio_write16
io_write_byte --> pio_write8
io_read_long  --> pio_read32
io_read_word  --> pio_read16
io_read_byte  --> pio_read8
io_write      --> pio_write
io_read       --> pio_read

setl --> set32
setw --> set16
setb --> set8

igned-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
This commit is contained in:
Mingqiang Chi
2018-08-01 18:19:08 +08:00
committed by lijinxia
parent 7db4c0aac9
commit 61782d7430
12 changed files with 64 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/debug/reboot.c
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@@ -7,6 +7,6 @@
int warm_reboot(void)
{
io_write_byte(0x6, 0xcf9);
pio_write8(0x6, 0xcf9);
return 0;
}

4
hypervisor/arch/x86/guest/pm.c
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@@ -137,7 +137,7 @@ static inline uint8_t get_slp_typx(uint32_t pm1_cnt)
static uint32_t pm1ab_io_read(__unused struct vm_io_handler *hdlr,
__unused struct vm *vm, uint16_t addr, size_t width)
{
uint32_t val = io_read(addr, width);
uint32_t val = pio_read(addr, width);
if (host_enter_s3_success == 0U) {
/* If host S3 enter failes, we should set BIT_WAK_STS
@@ -186,7 +186,7 @@ static void pm1ab_io_write(__unused struct vm_io_handler *hdlr,
}
}
io_write(v, addr, width);
pio_write(v, addr, width);
}
static void

8
hypervisor/arch/x86/ioapic.c
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@@ -99,9 +99,9 @@ ioapic_read_reg32(const void *ioapic_base, const uint32_t offset)
spinlock_irqsave_obtain(&ioapic_lock);
/* Write IOREGSEL */
mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
mmio_write32(offset, (void *)ioapic_base + IOAPIC_REGSEL);
/* Read IOWIN */
v = mmio_read_long((void *)ioapic_base + IOAPIC_WINDOW);
v = mmio_read32((void *)ioapic_base + IOAPIC_WINDOW);
spinlock_irqrestore_release(&ioapic_lock);
return v;
@@ -116,9 +116,9 @@ ioapic_write_reg32(const void *ioapic_base,
spinlock_irqsave_obtain(&ioapic_lock);
/* Write IOREGSEL */
mmio_write_long(offset, (void *)ioapic_base + IOAPIC_REGSEL);
mmio_write32(offset, (void *)ioapic_base + IOAPIC_REGSEL);
/* Write IOWIN */
mmio_write_long(value, (void *)ioapic_base + IOAPIC_WINDOW);
mmio_write32(value, (void *)ioapic_base + IOAPIC_WINDOW);
spinlock_irqrestore_release(&ioapic_lock);
}

4
hypervisor/arch/x86/irq.c
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@@ -157,8 +157,8 @@ static void _irq_desc_free_vector(uint32_t irq)
static void disable_pic_irq(void)
{
io_write_byte(0xffU, 0xA1U);
io_write_byte(0xffU, 0x21U);
pio_write8(0xffU, 0xA1U);
pio_write8(0xffU, 0x21U);
}
static bool

4
hypervisor/arch/x86/lapic.c
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@@ -143,7 +143,7 @@ static inline uint32_t read_lapic_reg32(uint32_t offset)
if (offset < 0x20U || offset > 0x3ffU)
return 0;
return mmio_read_long(lapic_info.xapic.vaddr + offset);
return mmio_read32(lapic_info.xapic.vaddr + offset);
}
inline void write_lapic_reg32(uint32_t offset, uint32_t value)
@@ -151,7 +151,7 @@ inline void write_lapic_reg32(uint32_t offset, uint32_t value)
if (offset < 0x20U || offset > 0x3ffU)
return;
mmio_write_long(value, lapic_info.xapic.vaddr + offset);
mmio_write32(value, lapic_info.xapic.vaddr + offset);
}
static void clear_lapic_isr(void)

8
hypervisor/arch/x86/pm.c
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@@ -24,9 +24,9 @@ static void acpi_gas_write(struct acpi_generic_address *gas, uint32_t val)
uint16_t val16 = (uint16_t)val;
if (gas->space_id == SPACE_SYSTEM_MEMORY)
mmio_write_word(val16, HPA2HVA(gas->address));
mmio_write16(val16, HPA2HVA(gas->address));
else
io_write_word(val16, (uint16_t)gas->address);
pio_write16(val16, (uint16_t)gas->address);
}
static uint32_t acpi_gas_read(struct acpi_generic_address *gas)
@@ -34,9 +34,9 @@ static uint32_t acpi_gas_read(struct acpi_generic_address *gas)
uint32_t ret = 0U;
if (gas->space_id == SPACE_SYSTEM_MEMORY)
ret = mmio_read_word(HPA2HVA(gas->address));
ret = mmio_read16(HPA2HVA(gas->address));
else
ret = io_read_word((uint16_t)gas->address);
ret = pio_read16((uint16_t)gas->address);
return ret;
}

12
hypervisor/arch/x86/timer.c
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@@ -261,9 +261,9 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms_arg)
* Read/Write least significant byte first, mode 0, 16 bits.
*/
io_write_byte(0x30U, 0x43U);
io_write_byte(initial_pit_low, 0x40U); /* Write LSB */
io_write_byte(initial_pit_high, 0x40U); /* Write MSB */
pio_write8(0x30U, 0x43U);
pio_write8(initial_pit_low, 0x40U); /* Write LSB */
pio_write8(initial_pit_high, 0x40U); /* Write MSB */
current_tsc = rdtsc();
@@ -271,10 +271,10 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms_arg)
/* Port 0x43 ==> Control word write; 0x00 ==> Select
* Counter 0, Counter Latch Command, Mode 0; 16 bits
*/
io_write_byte(0x00U, 0x43U);
pio_write8(0x00U, 0x43U);
current_pit = io_read_byte(0x40U); /* Read LSB */
current_pit |= io_read_byte(0x40U) << 8U; /* Read MSB */
current_pit = pio_read8(0x40U); /* Read LSB */
current_pit |= pio_read8(0x40U) << 8U; /* Read MSB */
/* Let the counter count down to PIT_TARGET */
} while (current_pit > PIT_TARGET);

10
hypervisor/arch/x86/virq.c
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@@ -182,11 +182,11 @@ void dump_lapic(void)
{
dev_dbg(ACRN_DBG_INTR,
"LAPIC: TIME %08x, init=0x%x cur=0x%x ISR=0x%x IRR=0x%x",
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
mmio_read32(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
}
/* SDM Vol3 -6.15, Table 6-4 - interrupt and exception classes */

12
hypervisor/arch/x86/vtd.c
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@@ -191,16 +191,16 @@ static void register_hrhd_units(void)
static uint32_t iommu_read32(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
{
return mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
return mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
}
static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
{
uint64_t value;
value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
value = mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
value = value << 32U;
value = value | mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr +
value = value | mmio_read32(HPA2HVA(dmar_uint->drhd->reg_base_addr +
offset));
return value;
@@ -209,7 +209,7 @@ static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
static void iommu_write32(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
uint32_t value)
{
mmio_write_long(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
mmio_write32(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
}
static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
@@ -218,10 +218,10 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
uint32_t temp;
temp = (uint32_t)value;
mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
temp = (uint32_t)(value >> 32U);
mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
mmio_write32(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
}
/* flush cache when root table, context table updated */