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hv: add missing support to intercept x2APIC MSRs

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Accessing x2APIC MSRs in xAPIC mode should result in GP exception according
to SDM section 10.12.2. Adding support to ACRN to inject GP into guests for
the same reason.

Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This commit is contained in:
Sainath Grandhi
2018-11-01 13:59:37 -07:00
committed by lijinxia
parent 94dadc1d14
commit 64f61961bf
3 changed files with 139 additions and 17 deletions
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12
hypervisor/include/arch/x86/msr.h
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@@ -529,6 +529,18 @@ static inline bool pat_mem_type_invalid(uint64_t x)
(x != PAT_MEM_TYPE_WT) && (x != PAT_MEM_TYPE_WP) &&
(x != PAT_MEM_TYPE_WB) && (x != PAT_MEM_TYPE_UCM));
}
static inline bool is_x2apic_msr(uint32_t msr)
{
bool ret = false;
/*
* if msr is in the range of x2APIC MSRs
*/
if ((msr >= MSR_IA32_EXT_XAPICID) && (msr <= MSR_IA32_EXT_APIC_SELF_IPI)) {
ret = true;
}
return ret;
}
#endif /* ASSEMBLER */
/* 5 high-order bits in every field are reserved */