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hv: vpci: trap PCIe ECAM access for SOS

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SOS will use PCIe ECAM access PCIe external configuration space. HV should trap this
access for security(Now pre-launched VM doesn't want to support PCI ECAM; post-launched
VM trap PCIe ECAM access in DM).
Besides, update PCIe MMCONFIG region to be owned by hypervisor and expose and pass through
platform hide PCI devices by BIOS to SOS.

Tracked-On: #3475
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
2019-12-05 22:51:06 +08:00
committed by wenlingz
parent 1e50ec8899
commit 65ed6c3529
6 changed files with 82 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
hypervisor/include/dm/vpci.h
View File

@@ -70,9 +70,9 @@ struct pci_msix {
};
union pci_cfgdata {
uint8_t data_8[PCI_REGMAX + 1U];
uint16_t data_16[(PCI_REGMAX + 1U) >> 1U];
uint32_t data_32[(PCI_REGMAX + 1U) >> 2U];
uint8_t data_8[PCIE_CONFIG_SPACE_SIZE];
uint16_t data_16[PCIE_CONFIG_SPACE_SIZE >> 1U];
uint32_t data_32[PCIE_CONFIG_SPACE_SIZE >> 2U];
};
struct pci_vdev;
@@ -123,6 +123,7 @@ struct acrn_vpci {
spinlock_t lock;
struct acrn_vm *vm;
union pci_cfg_addr_reg addr;
uint64_t pci_mmcfg_base;
uint32_t pci_vdev_cnt;
struct pci_vdev pci_vdevs[CONFIG_MAX_PCI_DEV_NUM];
};

6
hypervisor/include/hw/pci.h
View File

@@ -48,9 +48,12 @@
#define PCI_SLOTMAX 0x1FU
#define PCI_FUNCMAX 0x7U
#define PCI_BAR_COUNT 0x6U
#define PCI_REGMAX 0xFFU
#define PCI_REGMASK 0xFCU
#define PCI_CONFIG_SPACE_SIZE 0x100U
#define PCIE_CONFIG_SPACE_SIZE 0x1000U
#define PCI_MMCONFIG_SIZE 0x10000000U
/* I/O ports */
#define PCI_CONFIG_ADDR 0xCF8U
#define PCI_CONFIG_DATA 0xCFCU
@@ -323,6 +326,7 @@ static inline bool is_pci_cfg_bridge(uint8_t header_type)
return ((header_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE);
}
bool is_plat_hidden_pdev(union pci_bdf bdf);
bool pdev_need_bar_restore(const struct pci_pdev *pdev);
void pdev_restore_bar(const struct pci_pdev *pdev);
void pci_switch_to_mmio_cfg_ops(void);