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https://github.com/projectacrn/acrn-hypervisor.git
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hv: vpic: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule. Reduce the count of the "return entries". Fix the violations which is comply with the cases list below: 1.Function has 2 return entries. 2.The first return entry is used to return the error code of checking variable whether is valid. Fix the violations in "if else" format. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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17a6d9446e
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667e0444a9
@ -35,12 +35,15 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, uint8_t level
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static inline bool master_pic(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259)
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static inline bool master_pic(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259)
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{
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{
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bool ret;
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if (i8259 == &vpic->i8259[0]) {
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if (i8259 == &vpic->i8259[0]) {
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return true;
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ret = true;
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} else {
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} else {
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return false;
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ret = false;
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}
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}
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return ret;
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}
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}
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static inline uint8_t vpic_get_highest_isrpin(const struct i8259_reg_state *i8259)
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static inline uint8_t vpic_get_highest_isrpin(const struct i8259_reg_state *i8259)
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@ -207,8 +210,10 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
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}
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}
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}
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}
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static int vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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static int32_t vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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{
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int32_t ret;
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw1 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw1 0x%x\n",
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vpic->vm, val);
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vpic->vm, val);
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@ -224,17 +229,16 @@ static int vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259
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if ((val & ICW1_SNGL) != 0) {
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if ((val & ICW1_SNGL) != 0) {
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dev_dbg(ACRN_DBG_PIC, "vpic cascade mode required\n");
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dev_dbg(ACRN_DBG_PIC, "vpic cascade mode required\n");
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return -1;
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ret = -1;
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}
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} else if ((val & ICW1_IC4) == 0U) {
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if ((val & ICW1_IC4) == 0U) {
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dev_dbg(ACRN_DBG_PIC, "vpic icw4 required\n");
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dev_dbg(ACRN_DBG_PIC, "vpic icw4 required\n");
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return -1;
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ret = -1;
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} else {
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i8259->icw_num++;
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ret = 0;
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}
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}
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i8259->icw_num++;
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return ret;
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return 0;
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}
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}
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static int vpic_icw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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static int vpic_icw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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@ -259,17 +263,18 @@ static int vpic_icw3(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259
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return 0;
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return 0;
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}
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}
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static int vpic_icw4(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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static int32_t vpic_icw4(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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{
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int32_t ret;
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw4 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw4 0x%x\n",
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vpic->vm, val);
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vpic->vm, val);
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if ((val & ICW4_8086) == 0U) {
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if ((val & ICW4_8086) == 0U) {
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dev_dbg(ACRN_DBG_PIC,
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dev_dbg(ACRN_DBG_PIC,
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"vpic microprocessor mode required\n");
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"vpic microprocessor mode required\n");
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return -1;
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ret = -1;
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}
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} else {
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if ((val & ICW4_AEOI) != 0U) {
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if ((val & ICW4_AEOI) != 0U) {
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i8259->aeoi = true;
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i8259->aeoi = true;
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}
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}
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@ -286,8 +291,10 @@ static int vpic_icw4(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259
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i8259->icw_num = 0U;
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i8259->icw_num = 0U;
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i8259->ready = true;
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i8259->ready = true;
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ret = 0;
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}
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return 0;
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return ret;
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}
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}
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static int vpic_ocw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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static int vpic_ocw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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@ -405,10 +412,7 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin,
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uint8_t old_lvl;
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uint8_t old_lvl;
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bool lvl_trigger;
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bool lvl_trigger;
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if (pin >= NR_VPIC_PINS_TOTAL) {
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if (pin < NR_VPIC_PINS_TOTAL) {
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return;
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}
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i8259 = &vpic->i8259[pin >> 3U];
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i8259 = &vpic->i8259[pin >> 3U];
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old_lvl = i8259->pin_state[pin & 0x7U];
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old_lvl = i8259->pin_state[pin & 0x7U];
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if (level != 0U) {
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if (level != 0U) {
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@ -434,6 +438,7 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin,
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dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: %s, ignored\n",
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dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: %s, ignored\n",
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pin, (level != 0U) ? "asserted" : "deasserted");
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pin, (level != 0U) ? "asserted" : "deasserted");
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}
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}
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}
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}
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}
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/**
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/**
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@ -547,13 +552,11 @@ void vpic_pending_intr(struct acrn_vm *vm, uint32_t *vecptr)
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*/
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*/
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if (pin >= NR_VPIC_PINS_PER_CHIP) {
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if (pin >= NR_VPIC_PINS_PER_CHIP) {
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*vecptr = VECTOR_INVALID;
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*vecptr = VECTOR_INVALID;
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spinlock_release(&(vpic->lock));
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} else {
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return;
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}
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*vecptr = i8259->irq_base + pin;
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*vecptr = i8259->irq_base + pin;
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dev_dbg(ACRN_DBG_PIC, "Got pending vector 0x%x\n", *vecptr);
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dev_dbg(ACRN_DBG_PIC, "Got pending vector 0x%x\n", *vecptr);
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}
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spinlock_release(&(vpic->lock));
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spinlock_release(&(vpic->lock));
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}
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}
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@ -698,24 +701,25 @@ static int vpic_write(struct acrn_vpic *vpic, struct i8259_reg_state *i8259,
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return error;
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return error;
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}
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}
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static int vpic_master_handler(struct acrn_vm *vm, bool in, uint16_t port,
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static int32_t vpic_master_handler(struct acrn_vm *vm, bool in, uint16_t port,
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size_t bytes, uint32_t *eax)
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size_t bytes, uint32_t *eax)
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{
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{
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struct acrn_vpic *vpic;
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struct acrn_vpic *vpic;
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struct i8259_reg_state *i8259;
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struct i8259_reg_state *i8259;
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int32_t ret;
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vpic = vm_pic(vm);
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vpic = vm_pic(vm);
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i8259 = &vpic->i8259[0];
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i8259 = &vpic->i8259[0];
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if (bytes != 1U) {
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if (bytes != 1U) {
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return -1;
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ret = -1;
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} else if (in) {
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ret = vpic_read(vpic, i8259, port, eax);
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} else {
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ret = vpic_write(vpic, i8259, port, eax);
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}
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}
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if (in) {
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return ret;
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return vpic_read(vpic, i8259, port, eax);
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}
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return vpic_write(vpic, i8259, port, eax);
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}
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}
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static uint32_t vpic_master_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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static uint32_t vpic_master_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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@ -740,24 +744,25 @@ static void vpic_master_io_write(struct acrn_vm *vm, uint16_t addr, size_t width
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}
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}
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}
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}
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static int vpic_slave_handler(struct acrn_vm *vm, bool in, uint16_t port,
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static int32_t vpic_slave_handler(struct acrn_vm *vm, bool in, uint16_t port,
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size_t bytes, uint32_t *eax)
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size_t bytes, uint32_t *eax)
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{
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{
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struct acrn_vpic *vpic;
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struct acrn_vpic *vpic;
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struct i8259_reg_state *i8259;
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struct i8259_reg_state *i8259;
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int32_t ret;
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vpic = vm_pic(vm);
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vpic = vm_pic(vm);
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i8259 = &vpic->i8259[1];
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i8259 = &vpic->i8259[1];
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if (bytes != 1U) {
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if (bytes != 1U) {
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return -1;
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ret = -1;
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} else if (in) {
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ret = vpic_read(vpic, i8259, port, eax);
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} else {
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ret = vpic_write(vpic, i8259, port, eax);
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}
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}
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if (in) {
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return ret;
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return vpic_read(vpic, i8259, port, eax);
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}
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return vpic_write(vpic, i8259, port, eax);
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}
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}
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static uint32_t vpic_slave_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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static uint32_t vpic_slave_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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@ -782,19 +787,17 @@ static void vpic_slave_io_write(struct acrn_vm *vm, uint16_t addr, size_t width,
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}
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}
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}
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}
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static int vpic_elc_handler(struct acrn_vm *vm, bool in, uint16_t port, size_t bytes,
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static int32_t vpic_elc_handler(struct acrn_vm *vm, bool in, uint16_t port, size_t bytes,
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uint32_t *eax)
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uint32_t *eax)
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{
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{
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struct acrn_vpic *vpic;
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struct acrn_vpic *vpic;
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bool is_master;
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bool is_master;
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int32_t ret;
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vpic = vm_pic(vm);
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vpic = vm_pic(vm);
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is_master = (port == IO_ELCR1);
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is_master = (port == IO_ELCR1);
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if (bytes != 1U) {
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if (bytes == 1U) {
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return -1;
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}
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spinlock_obtain(&(vpic->lock));
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spinlock_obtain(&(vpic->lock));
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if (in) {
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if (in) {
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@ -822,8 +825,12 @@ static int vpic_elc_handler(struct acrn_vm *vm, bool in, uint16_t port, size_t b
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}
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}
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spinlock_release(&(vpic->lock));
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spinlock_release(&(vpic->lock));
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ret = 0;
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} else {
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ret = -1;
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}
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return 0;
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return ret;
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}
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}
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static uint32_t vpic_elc_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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static uint32_t vpic_elc_io_read(struct acrn_vm *vm, uint16_t addr, size_t width)
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