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hv: treewide: convert some MACROs to inline functions

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MISRA-C requires that each parameter in the MACRO shall be in brackets.

In some cases, adding brackets for all of the parameters may not be a
perfect solution.
For example, it may affect the code readability when there are many
parameters used in the MACRO.
And duplicated brackets will appear when one MACRO called another MACRO
which is using same parameters.

This patch convert some MACROs to inline functions to avoid such cases.

v1 -> v2:
 * Remove the unnecessary changes in hypervisor/bsp/uefi/efi/boot.h

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Shiqing Gao
2018-09-03 16:24:20 +08:00
committed by lijinxia
parent 37fd3871b7
commit 67038794af
6 changed files with 116 additions and 76 deletions
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54
hypervisor/include/arch/x86/cpu.h
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@@ -349,22 +349,22 @@ void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
}
/* Read MSR */
#define CPU_MSR_READ(reg, msr_val_ptr) \
{ \
uint32_t msrl, msrh; \
asm volatile (" rdmsr ":"=a"(msrl), \
"=d"(msrh) : "c" (reg)); \
*msr_val_ptr = ((uint64_t)msrh<<32) | msrl; \
static inline void cpu_msr_read(uint32_t reg, uint64_t *msr_val_ptr)
{
uint32_t msrl, msrh;
asm volatile (" rdmsr ":"=a"(msrl), "=d"(msrh) : "c" (reg));
*msr_val_ptr = ((uint64_t)msrh << 32U) | msrl;
}
/* Write MSR */
#define CPU_MSR_WRITE(reg, msr_val) \
{ \
uint32_t msrl, msrh; \
msrl = (uint32_t)msr_val; \
msrh = (uint32_t)(msr_val >> 32); \
asm volatile (" wrmsr " : : "c" (reg), \
"a" (msrl), "d" (msrh)); \
static inline void cpu_msr_write(uint32_t reg, uint64_t msr_val)
{
uint32_t msrl, msrh;
msrl = (uint32_t)msr_val;
msrh = (uint32_t)(msr_val >> 32U);
asm volatile (" wrmsr " : : "c" (reg), "a" (msrl), "d" (msrh));
}
#ifdef CONFIG_PARTITION_MODE
@@ -388,10 +388,11 @@ void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
#endif
/* This macro writes the stack pointer. */
#define CPU_SP_WRITE(stack_ptr) \
{ \
uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1UL); \
asm volatile ("movq %0, %%rsp" : : "r"(rsp)); \
static inline void cpu_sp_write(uint64_t *stack_ptr)
{
uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1UL);
asm volatile ("movq %0, %%rsp" : : "r"(rsp));
}
/* Synchronizes all read accesses from memory */
@@ -419,12 +420,13 @@ void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
}
/* Read time-stamp counter / processor ID */
#define CPU_RDTSCP_EXECUTE(timestamp_ptr, cpu_id_ptr) \
{ \
uint32_t tsl, tsh; \
asm volatile ("rdtscp":"=a"(tsl), "=d"(tsh), \
"=c"(*cpu_id_ptr)); \
*timestamp_ptr = ((uint64_t)tsh << 32) | tsl; \
static inline void
cpu_rdtscp_execute(uint64_t *timestamp_ptr, uint32_t *cpu_id_ptr)
{
uint32_t tsl, tsh;
asm volatile ("rdtscp":"=a"(tsl), "=d"(tsh), "=c"(*cpu_id_ptr));
*timestamp_ptr = ((uint64_t)tsh << 32U) | tsl;
}
/* Macro to save rflags register */
@@ -500,21 +502,19 @@ static inline uint64_t cpu_rbp_get(void)
return ret;
}
static inline uint64_t
msr_read(uint32_t reg_num)
{
uint64_t msr_val;
CPU_MSR_READ(reg_num, &msr_val);
cpu_msr_read(reg_num, &msr_val);
return msr_val;
}
static inline void
msr_write(uint32_t reg_num, uint64_t value64)
{
CPU_MSR_WRITE(reg_num, value64);
cpu_msr_write(reg_num, value64);
}
static inline void