From 67d06bc3a088d7cba9e00f8986810c7435dfcb23 Mon Sep 17 00:00:00 2001 From: dongshen Date: Thu, 10 Sep 2020 15:24:42 -0700 Subject: [PATCH] acrn-config: update configuration source code so that vm_configurations.h/vm_configurations.c are consistent for same scenario Tracked-On: #5229 Signed-off-by: dongshen --- misc/vm_configs/boards/ehl-crb-b/board_info.h | 5 -- .../scenarios/hybrid/ehl-crb-b/misc_cfg.h | 17 ++++ .../scenarios/hybrid/nuc7i7dnb/misc_cfg.h | 17 ++++ .../scenarios/hybrid/whl-ipc-i5/misc_cfg.h | 17 ++++ .../scenarios/hybrid/whl-ipc-i7/misc_cfg.h | 17 ++++ .../scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h | 17 ++++ .../scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h | 17 ++++ .../scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h | 17 ++++ .../scenarios/industry/ehl-crb-b/misc_cfg.h | 17 ++++ .../scenarios/industry/nuc7i7dnb/misc_cfg.h | 17 ++++ .../scenarios/industry/vm_configurations.c | 79 ------------------- .../scenarios/industry/vm_configurations.h | 4 +- .../scenarios/industry/whl-ipc-i5/misc_cfg.h | 17 ++++ .../scenarios/industry/whl-ipc-i7/misc_cfg.h | 17 ++++ .../logical_partition/nuc7i7dnb/misc_cfg.h | 17 ++++ .../logical_partition/whl-ipc-i5/misc_cfg.h | 17 ++++ .../logical_partition/whl-ipc-i7/misc_cfg.h | 17 ++++ 17 files changed, 240 insertions(+), 86 deletions(-) diff --git a/misc/vm_configs/boards/ehl-crb-b/board_info.h b/misc/vm_configs/boards/ehl-crb-b/board_info.h index 766e3c8f1..d71ce467e 100644 --- a/misc/vm_configs/boards/ehl-crb-b/board_info.h +++ b/misc/vm_configs/boards/ehl-crb-b/board_info.h @@ -15,11 +15,6 @@ #define HI_MMIO_END 0UL #define HI_MMIO_SIZE 0x10000000UL -#define P2SB_VGPIO_DM_ENABLED -#define P2SB_BAR_ADDR 0xFD000000UL -#define P2SB_BAR_ADDR_GPA 0xFD000000UL -#define P2SB_BAR_SIZE 0x1000000UL - #define P2SB_BASE_GPIO_PORT_ID 0x69U #define P2SB_MAX_GPIO_COMMUNITIES 0x6U diff --git a/misc/vm_configs/scenarios/hybrid/ehl-crb-b/misc_cfg.h b/misc/vm_configs/scenarios/hybrid/ehl-crb-b/misc_cfg.h index f918086a9..6d308fc2e 100644 --- a/misc/vm_configs/scenarios/hybrid/ehl-crb-b/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid/ehl-crb-b/misc_cfg.h @@ -31,8 +31,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #define CLOS_MASK_0 0xfffU diff --git a/misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h b/misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h index c5242c62e..f50932532 100644 --- a/misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h @@ -32,8 +32,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h b/misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h index 3fe908c03..ac820c700 100644 --- a/misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h @@ -32,8 +32,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h index 3fe908c03..ac820c700 100644 --- a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h @@ -32,8 +32,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h b/misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h index b7c7ed63f..6ce2fd09d 100644 --- a/misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid_rt/ehl-crb-b/misc_cfg.h @@ -31,8 +31,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #define CLOS_MASK_0 0xfffU diff --git a/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h b/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h index 05a124efb..8730b8e02 100644 --- a/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h @@ -32,8 +32,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h index 05a124efb..8730b8e02 100644 --- a/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h +++ b/misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h @@ -32,8 +32,25 @@ #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h b/misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h index 8d3a1064c..3b4819154 100644 --- a/misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h +++ b/misc/vm_configs/scenarios/industry/ehl-crb-b/misc_cfg.h @@ -36,8 +36,25 @@ #define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 16U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 16U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 16U #define CLOS_MASK_0 0xfffU diff --git a/misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h b/misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h index 6fb849f6f..27a6d91e6 100644 --- a/misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h +++ b/misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h @@ -37,8 +37,25 @@ #define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/industry/vm_configurations.c b/misc/vm_configs/scenarios/industry/vm_configurations.c index 5105d5051..9418f9f1b 100644 --- a/misc/vm_configs/scenarios/industry/vm_configurations.c +++ b/misc/vm_configs/scenarios/industry/vm_configurations.c @@ -78,83 +78,4 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = { .t_vuart.vuart_id = 1U, }, }, - { /* VM3 */ - CONFIG_POST_STD_VM(2), -#ifdef CONFIG_RDT_ENABLED - .clos = VM3_VCPU_CLOS, -#endif - .cpu_affinity = VM3_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - }, - { /* VM4 */ - CONFIG_POST_STD_VM(3), -#ifdef CONFIG_RDT_ENABLED - .clos = VM4_VCPU_CLOS, -#endif - .cpu_affinity = VM4_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - }, - { /* VM5 */ - CONFIG_POST_STD_VM(4), -#ifdef CONFIG_RDT_ENABLED - .clos = VM5_VCPU_CLOS, -#endif - .cpu_affinity = VM5_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - }, - { /* VM6 */ - CONFIG_POST_STD_VM(5), -#ifdef CONFIG_RDT_ENABLED - .clos = VM6_VCPU_CLOS, -#endif - .cpu_affinity = VM6_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = COM1_BASE, - .irq = COM1_IRQ, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - }, - { /* VM7 */ - CONFIG_KATA_VM(1), -#ifdef CONFIG_RDT_ENABLED - .clos = VM7_VCPU_CLOS, -#endif - .cpu_affinity = VM7_CONFIG_CPU_AFFINITY, - .vuart[0] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - .vuart[1] = { - .type = VUART_LEGACY_PIO, - .addr.port_base = INVALID_COM_BASE, - }, - }, }; diff --git a/misc/vm_configs/scenarios/industry/vm_configurations.h b/misc/vm_configs/scenarios/industry/vm_configurations.h index 088f63373..49e71f829 100644 --- a/misc/vm_configs/scenarios/industry/vm_configurations.h +++ b/misc/vm_configs/scenarios/industry/vm_configurations.h @@ -15,8 +15,8 @@ */ #define PRE_VM_NUM 0U #define SOS_VM_NUM 1U -#define MAX_POST_VM_NUM 7U -#define CONFIG_MAX_KATA_VM_NUM 1U +#define MAX_POST_VM_NUM 2U +#define CONFIG_MAX_KATA_VM_NUM 0U /* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */ #define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \ diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h b/misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h index 6fb849f6f..27a6d91e6 100644 --- a/misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h @@ -37,8 +37,25 @@ #define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h index 6fb849f6f..27a6d91e6 100644 --- a/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h @@ -37,8 +37,25 @@ #define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h b/misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h index 43c48a486..d390a1bf4 100644 --- a/misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h +++ b/misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h @@ -11,8 +11,25 @@ #define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h index f0dea5315..3b4959d90 100644 --- a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h @@ -11,8 +11,25 @@ #define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h index f0dea5315..3b4959d90 100644 --- a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h @@ -11,8 +11,25 @@ #define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U)) #ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ #define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ #define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ #define MAX_CACHE_CLOS_NUM_ENTRIES 0U #endif