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https://github.com/projectacrn/acrn-hypervisor.git
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hv: fix '(void) missing for discarded return value'
MISRA-C requires that the function call in which the returned value is discarded shall be clearly indicated using (void). This patch fixes the violations related to the following function calls. - instr_check_gva - vlapic_set_local_intr - prepare_vm - enter_s3 - emulate_instruction - ptdev_intx_pin_remap - register_mmio_emulation_handler v1 -> v2: * discard the return value of enter_s3 Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
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@ -513,7 +513,7 @@ static void bsp_boot_post(void)
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exec_vmxon_instr(BOOT_CPU_ID);
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prepare_vm(BOOT_CPU_ID);
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(void)prepare_vm(BOOT_CPU_ID);
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default_idle();
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@ -583,7 +583,7 @@ static void cpu_secondary_post(void)
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exec_vmxon_instr(get_cpu_id());
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#ifdef CONFIG_PARTITION_MODE
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prepare_vm(get_cpu_id());
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(void)prepare_vm(get_cpu_id());
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#endif
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default_idle();
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@ -2293,7 +2293,10 @@ int decode_instruction(struct acrn_vcpu *vcpu)
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return retval;
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}
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} else {
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instr_check_gva(vcpu, emul_ctxt, cpu_mode);
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retval = instr_check_gva(vcpu, emul_ctxt, cpu_mode);
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if (retval < 0) {
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return retval;
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}
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}
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return (int)(emul_ctxt->vie.opsize);
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@ -83,7 +83,7 @@ void emulate_mmio_post(const struct acrn_vcpu *vcpu, const struct io_request *io
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if (mmio_req->direction == REQUEST_READ) {
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/* Emulate instruction and update vcpu register set */
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emulate_instruction(vcpu);
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(void)emulate_instruction(vcpu);
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}
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}
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@ -123,8 +123,7 @@ void do_acpi_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val,
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}
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}
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int enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val,
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uint32_t pm1b_cnt_val)
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void enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val)
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{
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uint64_t pmain_entry_saved;
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uint32_t guest_wakeup_vec32;
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@ -135,7 +134,7 @@ int enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val,
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if (vm->pm.sx_state_data == NULL) {
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pr_err("No Sx state info avaiable. No Sx support");
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host_enter_s3_success = 0U;
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return -1;
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return;
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}
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pause_vm(vm); /* pause vm0 before suspend system */
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@ -193,5 +192,5 @@ int enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val,
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/* jump back to vm */
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resume_vm_from_s3(vm, guest_wakeup_vec32);
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return 0;
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return;
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}
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@ -401,7 +401,7 @@ vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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((last.full & IOAPIC_RTE_INTMASK) == 0UL)) {
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/* VM enable intr */
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/* NOTE: only support max 256 pin */
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ptdev_intx_pin_remap(vioapic->vm,
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(void)ptdev_intx_pin_remap(vioapic->vm,
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(uint8_t)pin, PTDEV_VPIN_IOAPIC);
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}
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}
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@ -516,7 +516,7 @@ vioapic_init(struct acrn_vm *vm)
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vioapic_reset(vm_ioapic(vm));
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register_mmio_emulation_handler(vm,
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(void)register_mmio_emulation_handler(vm,
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vioapic_mmio_access_handler,
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(uint64_t)VIOAPIC_BASE,
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(uint64_t)VIOAPIC_BASE + VIOAPIC_SIZE,
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@ -192,7 +192,11 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
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struct acrn_vcpu *vcpu = vcpu_from_vid(vpic->vm, 0U);
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vcpu_inject_extint(vcpu);
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} else {
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vlapic_set_local_intr(vpic->vm, BROADCAST_CPU_ID, APIC_LVT_LINT0);
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/*
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* The input parameters here guarantee the return value of vlapic_set_local_intr is 0, means
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* success.
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*/
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(void)vlapic_set_local_intr(vpic->vm, BROADCAST_CPU_ID, APIC_LVT_LINT0);
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/* notify vioapic pin0 if existing
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* For vPIC + vIOAPIC mode, vpic master irq connected
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* to vioapic pin0 (irq2)
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@ -321,7 +325,7 @@ static int vpic_ocw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259
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virt_pin = (master_pic(vpic, i8259)) ?
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pin : (pin + 8U);
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ptdev_intx_pin_remap(vpic->vm,
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(void)ptdev_intx_pin_remap(vpic->vm,
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virt_pin, PTDEV_VPIN_PIC);
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}
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pin = (pin + 1U) & 0x7U;
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@ -13,7 +13,7 @@ extern struct pm_s_state_data host_pm_s_state;
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extern uint8_t host_enter_s3_success;
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int enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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void enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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extern void asm_enter_s3(struct acrn_vm *vm, uint32_t pm1a_cnt_val,
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uint32_t pm1b_cnt_val);
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extern void restore_s3_context(void);
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