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Update pages with missing links
Signed-off-by: Deb Taylor <deb.taylor@intel.com> Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
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@@ -95,7 +95,7 @@ Memory
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interrupt stack table (IST) which are different across physical
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processors. LDT is disabled.
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Refer to section 3.5.2 for a detailed description of interrupt-related
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Refer to :ref:`physical-interrupt-initialization` for a detailed description of interrupt-related
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initial states, including IDT and physical PICs.
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After BSP detects that all APs are up, BSP will start creating the first
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