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hv: Bit Representation for IOAPIC RTE

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As we enable Interrupt Remapping, bit positions in IOAPIC RTEs
have a different syntax for programming. ACRN should handle original
format for vIOAPIC as well IR representation for physical IOAPIC.
This patch adds bit granularity IOAPIC RTE.

Tracked-On: #2407
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
This commit is contained in:
Sainath Grandhi
2019-01-26 01:33:02 -08:00
committed by wenlingz
parent 7d57eb056e
commit 6d5456a0df
8 changed files with 158 additions and 175 deletions
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77
hypervisor/include/arch/x86/apicreg.h
View File

@@ -166,6 +166,30 @@ struct ioapic {
uint32_t rsv1[3];
};
/*
* Macros for bits in union ioapic_rte
*/
#define IOAPIC_RTE_MASK_CLR 0x0U /* Interrupt Mask: Clear */
#define IOAPIC_RTE_MASK_SET 0x1U /* Interrupt Mask: Set */
#define IOAPIC_RTE_TRGRMODE_EDGE 0x0U /* Trigger Mode: Edge */
#define IOAPIC_RTE_TRGRMODE_LEVEL 0x1U /* Trigger Mode: Level */
#define IOAPIC_RTE_REM_IRR 0x1U /* Remote IRR: Read-Only */
#define IOAPIC_RTE_INTPOL_AHI 0x0U /* Interrupt Polarity: active high */
#define IOAPIC_RTE_INTPOL_ALO 0x1U /* Interrupt Polarity: active low */
#define IOAPIC_RTE_DELIVS 0x1U /* Delivery Status: Read-Only */
#define IOAPIC_RTE_DESTMODE_PHY 0x0U /* Destination Mode: Physical */
#define IOAPIC_RTE_DESTMODE_LOGICAL 0x1U /* Destination Mode: Logical */
#define IOAPIC_RTE_DELMODE_FIXED 0x0U /* Delivery Mode: Fixed */
#define IOAPIC_RTE_DELMODE_LOPRI 0x1U /* Delivery Mode: Lowest priority */
#define IOAPIC_RTE_DELMODE_INIT 0x5U /* Delivery Mode: INIT signal */
#define IOAPIC_RTE_DELMODE_EXINT 0x7U /* Delivery Mode: External INTerrupt */
/* IOAPIC Redirection Table (RTE) Entry structure */
union ioapic_rte {
uint64_t full;
@@ -173,6 +197,18 @@ union ioapic_rte {
uint32_t lo_32;
uint32_t hi_32;
} u;
struct {
uint64_t vector:8;
uint64_t delivery_mode:3;
uint64_t dest_mode:1;
uint64_t delivery_status:1;
uint64_t intr_polarity:1;
uint64_t remote_irr:1;
uint64_t trigger_mode:1;
uint64_t intr_mask:1;
uint64_t rsvd_1:39;
uint64_t dest_field:8;
} bits __packed;
};
/******************************************************************************
@@ -390,45 +426,4 @@ union ioapic_rte {
#define IOAPIC_MAX_RTE_MASK 0x00ff0000U
#define MAX_RTE_SHIFT 16U
/*
* fields in the IO APIC's redirection table entries
*/
#define IOAPIC_RTE_DEST_SHIFT 56U
/* broadcast addr: all APICs */
#define IOAPIC_RTE_DEST_MASK 0xff00000000000000UL
#define IOAPIC_RTE_RESV 0x00fe0000UL /* reserved */
#define IOAPIC_RTE_INTMASK 0x00010000UL /* R/W: INTerrupt mask */
#define IOAPIC_RTE_INTMCLR 0x00000000UL /* clear, allow INTs */
#define IOAPIC_RTE_INTMSET 0x00010000UL /* set, inhibit INTs */
#define IOAPIC_RTE_TRGRMOD 0x00008000UL /* R/W: trigger mode */
#define IOAPIC_RTE_TRGREDG 0x00000000UL /* edge */
#define IOAPIC_RTE_TRGRLVL 0x00008000UL /* level */
#define IOAPIC_RTE_REM_IRR 0x00004000UL /* RO: remote IRR */
#define IOAPIC_RTE_INTPOL 0x00002000UL /*R/W:INT input pin polarity*/
#define IOAPIC_RTE_INTAHI 0x00000000UL /* active high */
#define IOAPIC_RTE_INTALO 0x00002000UL /* active low */
#define IOAPIC_RTE_DELIVS 0x00001000UL /* RO: delivery status */
#define IOAPIC_RTE_DESTMOD 0x00000800UL /*R/W:destination mode*/
#define IOAPIC_RTE_DESTPHY 0x00000000UL /* physical */
#define IOAPIC_RTE_DESTLOG 0x00000800UL /* logical */
#define IOAPIC_RTE_DELMOD 0x00000700UL /* R/W: delivery mode */
#define IOAPIC_RTE_DELFIXED 0x00000000UL /* fixed */
#define IOAPIC_RTE_DELLOPRI 0x00000100UL /* lowest priority */
#define IOAPIC_RTE_DELSMI 0x00000200UL /*System Management INT*/
#define IOAPIC_RTE_DELRSV1 0x00000300UL /* reserved */
#define IOAPIC_RTE_DELNMI 0x00000400UL /* NMI signal */
#define IOAPIC_RTE_DELINIT 0x00000500UL /* INIT signal */
#define IOAPIC_RTE_DELRSV2 0x00000600UL /* reserved */
#define IOAPIC_RTE_DELEXINT 0x00000700UL /* External INTerrupt */
#define IOAPIC_RTE_INTVEC 0x000000ffUL /*R/W: INT vector field*/
#endif /* APICREG_H */

6
hypervisor/include/arch/x86/irq.h
View File

@@ -48,9 +48,9 @@
#define POSTED_INTR_NOTIFY_IRQ (NR_IRQS - 3U)
#define PMI_IRQ (NR_IRQS - 4U)
#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTLOG
#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELLOPRI
#define ALL_CPUS_MASK ((1UL << (uint64_t)get_pcpu_nums()) - 1UL)
#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTMODE_LOGICAL
#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELMODE_LOPRI
#define ALL_CPUS_MASK (uint32_t) (((uint32_t)1U << (uint32_t) get_pcpu_nums()) - (uint32_t)1U)
#define IRQ_ALLOC_BITMAP_SIZE INT_DIV_ROUNDUP(NR_IRQS, 64U)