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Revert "hv: Let trampoline execution use 1GB pages"

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This patch tries to release hardware platform 1GB large page support constrain
on CPU side.

There're some silicon bug on lakefield, TNT and EHL platforms which cause CPU
couldn't support 1GB large page. As a result, the pre-assumption The platform
which ACRN supports must support 1GB large page on both CPU side and VTD side
is not true any more.

This reverts commit f01aad7e to let trampoline execution use 2MB pages.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
2020-06-05 10:02:41 +08:00
committed by wenlingz
parent 0ad80d1f09
commit 6e57553015
2 changed files with 20 additions and 8 deletions
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19
hypervisor/arch/x86/boot/trampoline.S
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@@ -179,8 +179,7 @@ trampoline_gdt_ptr:
.short (trampoline_gdt_end - trampoline_gdt) - 1
.quad trampoline_gdt
/* PML4 and PDPT tables initialized to map first 4 GBytes of memory */
/* Assumes CPU supports 1GB large pages */
/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
.align 4
.global cpu_boot_page_tables_ptr
cpu_boot_page_tables_ptr:
@@ -198,9 +197,19 @@ cpu_boot_page_tables_start:
trampoline_pdpt_addr:
address = 0
.rept 4
/* 0x83 = (PAGE_PRESENT | PAGE_PSE | PAGE_RW) */
.quad address + 0x83
address = address + 0x40000000
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdt_addr + address + 0x3
/*0x1000 = PAGE_SIZE*/
address = address + 0x1000
.endr
/*0x1000 = PAGE_SIZE*/
.align 0x1000
trampoline_pdt_addr:
address = 0
.rept 2048
/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83
address = address + 0x200000
.endr
.end