diff --git a/hypervisor/arch/x86/guest/guest.c b/hypervisor/arch/x86/guest/guest.c
index dfb33bca3..ca187cfec 100644
--- a/hypervisor/arch/x86/guest/guest.c
+++ b/hypervisor/arch/x86/guest/guest.c
@@ -134,7 +134,7 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
 		if (pw_info->is_write_access && ((entry & MMU_32BIT_PDE_RW) == 0U)) {
 			/* Case1: Supermode and wp is 1
 			 * Case2: Usermode */
-			if (!(!pw_info->is_user_mode && !pw_info->wp)) {
+			if (pw_info->is_user_mode || pw_info->wp) {
 				fault = 1;
 			}
 		}
@@ -150,7 +150,7 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
 			fault = 1;
 		}
 
-		if (pw_info->pse && (i > 0U && ((entry & MMU_32BIT_PDE_PS) != 0U))) {
+		if (pw_info->pse && ((i > 0U) && ((entry & MMU_32BIT_PDE_PS) != 0U))) {
 			break;
 		}
 		addr = entry;
@@ -502,18 +502,18 @@ static void rebuild_vm0_e820(void)
 		entry_end = entry->baseaddr + entry->length;
 
 		/* No need handle in these cases*/
-		if (entry->type != E820_TYPE_RAM || entry_end <= hv_start
-				|| entry_start >= hv_end) {
+		if ((entry->type != E820_TYPE_RAM) || (entry_end <= hv_start)
+				|| (entry_start >= hv_end)) {
 			continue;
 		}
 
 		/* filter out hv mem and adjust length of this entry*/
-		if (entry_start < hv_start && entry_end <= hv_end) {
+		if ((entry_start < hv_start) && (entry_end <= hv_end)) {
 			entry->length = hv_start - entry_start;
 			continue;
 		}
 		/* filter out hv mem and need to create a new entry*/
-		if (entry_start < hv_start && entry_end > hv_end) {
+		if ((entry_start < hv_start) && (entry_end > hv_end)) {
 			entry->length = hv_start - entry_start;
 			new_entry.baseaddr = hv_end;
 			new_entry.length = entry_end - hv_end;
@@ -523,13 +523,13 @@ static void rebuild_vm0_e820(void)
 		/* This entry is within the range of hv mem
 		 * change to E820_TYPE_RESERVED
 		 */
-		if (entry_start >= hv_start && entry_end <= hv_end) {
+		if ((entry_start >= hv_start) && (entry_end <= hv_end)) {
 			entry->type = E820_TYPE_RESERVED;
 			continue;
 		}
 
-		if (entry_start >= hv_start && entry_start < hv_end
-				&& entry_end > hv_end) {
+		if ((entry_start >= hv_start) && (entry_start < hv_end)
+				&& (entry_end > hv_end)) {
 			entry->baseaddr = hv_end;
 			entry->length = entry_end - hv_end;
 			continue;
diff --git a/hypervisor/arch/x86/guest/instr_emul.c b/hypervisor/arch/x86/guest/instr_emul.c
index cf2438a7c..521f0d368 100644
--- a/hypervisor/arch/x86/guest/instr_emul.c
+++ b/hypervisor/arch/x86/guest/instr_emul.c
@@ -1628,7 +1628,7 @@ static int vie_init(struct instr_emul_vie *vie, struct vcpu *vcpu)
 	uint64_t fault_addr;
 	int ret;
 
-	if (inst_len > VIE_INST_SIZE || inst_len == 0U) {
+	if ((inst_len > VIE_INST_SIZE) || (inst_len == 0U)) {
 		pr_err("%s: invalid instruction length (%d)",
 			__func__, inst_len);
 		return -EINVAL;
@@ -1731,7 +1731,7 @@ static int decode_prefixes(struct instr_emul_vie *vie,
 	 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
 	 *   the mandatory prefix must come before the REX prefix.
 	 */
-	if (cpu_mode == CPU_MODE_64BIT && x >= 0x40U && x <= 0x4FU) {
+	if ((cpu_mode == CPU_MODE_64BIT) && (x >= 0x40U) && (x <= 0x4FU)) {
 		vie->rex_present = 1U;
 		vie->rex_w = (x & 0x8U) != 0U ? 1U : 0U;
 		vie->rex_r = (x & 0x4U) != 0U ? 1U : 0U;
@@ -1839,8 +1839,8 @@ static int decode_modrm(struct instr_emul_vie *vie, enum vm_cpu_mode cpu_mode)
 		return -1;
 	}
 
-	if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
-			(vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
+	if (((vie->mod == VIE_MOD_INDIRECT) && (vie->rm == VIE_RM_DISP32)) ||
+			((vie->mod != VIE_MOD_DIRECT) && (vie->rm == VIE_RM_SIB))) {
 		/*
 		 * Table 2-5: Special Cases of REX Encodings
 		 *
@@ -1869,7 +1869,7 @@ static int decode_sib(struct instr_emul_vie *vie)
 	uint8_t x;
 
 	/* Proceed only if SIB byte is present */
-	if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB) {
+	if ((vie->mod == VIE_MOD_DIRECT) || (vie->rm != VIE_RM_SIB)) {
 		return 0;
 	}
 
@@ -1908,8 +1908,8 @@ static int decode_sib(struct instr_emul_vie *vie)
 		break;
 	}
 
-	if (vie->mod == VIE_MOD_INDIRECT &&
-			(vie->base == 5U || vie->base == 13U)) {
+	if ((vie->mod == VIE_MOD_INDIRECT) &&
+			((vie->base == 5U) || (vie->base == 13U))) {
 		/*
 		 * Special case when base register is unused if mod = 0
 		 * and base = %rbp or %r13.
@@ -1960,7 +1960,7 @@ static int decode_displacement(struct instr_emul_vie *vie)
 		return 0;
 	}
 
-	if (n != 1 && n != 4) {
+	if ((n != 1) && (n != 4)) {
 		pr_err("%s: decode_displacement: invalid disp_bytes %d",
 			__func__, n);
 		return -EINVAL;
@@ -2004,7 +2004,7 @@ static int decode_immediate(struct instr_emul_vie *vie)
 		 * processor sign-extends all immediates to 64-bits prior
 		 * to their use.
 		 */
-		if (vie->opsize == 4U || vie->opsize == 8U) {
+		if ((vie->opsize == 4U) || (vie->opsize == 8U)) {
 			vie->imm_bytes = 4U;
 		}
 		else {
@@ -2021,7 +2021,7 @@ static int decode_immediate(struct instr_emul_vie *vie)
 		return 0;
 	}
 
-	if ( n != 1 && n != 2 && n != 4) {
+	if ((n != 1) && (n != 2) && (n != 4)) {
 		pr_err("%s: invalid number of immediate bytes: %d",
 			__func__, n);
 		return -EINVAL;
@@ -2065,7 +2065,7 @@ static int decode_moffset(struct instr_emul_vie *vie)
 	 * The memory offset size follows the address-size of the instruction.
 	 */
 	n = vie->addrsize;
-	if ( n != 2U && n != 4U && n != 8U) {
+	if ((n != 2U) && (n != 4U) && (n != 8U)) {
 		pr_err("%s: invalid moffset bytes: %hhu", __func__, n);
 		return -EINVAL;
 	}
diff --git a/hypervisor/arch/x86/guest/pm.c b/hypervisor/arch/x86/guest/pm.c
index e3058e76e..c34ad6020 100644
--- a/hypervisor/arch/x86/guest/pm.c
+++ b/hypervisor/arch/x86/guest/pm.c
@@ -18,7 +18,7 @@ int validate_pstate(struct vm *vm, uint64_t perf_ctl)
 	px_cnt = vm->pm.px_cnt;
 	px_data = vm->pm.px_data;
 
-	if (px_cnt == 0 || px_data == NULL) {
+	if ((px_cnt == 0) || (px_data == NULL)) {
 		return -1;
 	}
 
diff --git a/hypervisor/arch/x86/guest/vlapic.c b/hypervisor/arch/x86/guest/vlapic.c
index 35be79c0a..567270f78 100644
--- a/hypervisor/arch/x86/guest/vlapic.c
+++ b/hypervisor/arch/x86/guest/vlapic.c
@@ -305,7 +305,7 @@ set_expiration(struct acrn_vlapic *vlapic)
 	tmicr = vtimer->tmicr;
 	divisor_shift = vtimer->divisor_shift;
 
-	if (!tmicr || divisor_shift > 8U) {
+	if (!tmicr || (divisor_shift > 8U)) {
 		return false;
 	}
 
@@ -610,14 +610,14 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
 	val &= mask;
 
 	/* vlapic mask/unmask LINT0 for ExtINT? */
-	if (offset == APIC_OFFSET_LINT0_LVT &&
+	if ((offset == APIC_OFFSET_LINT0_LVT) &&
 		((val & APIC_LVT_DM) == APIC_LVT_DM_EXTINT)) {
 		uint32_t last = vlapic_get_lvt(vlapic, offset);
 
 		/* mask -> unmask: may from every vlapic in the vm */
 		if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0U)) {
-			if (vlapic->vm->wire_mode == VPIC_WIRE_INTR ||
-				vlapic->vm->wire_mode == VPIC_WIRE_NULL) {
+			if ((vlapic->vm->wire_mode == VPIC_WIRE_INTR) ||
+				(vlapic->vm->wire_mode == VPIC_WIRE_NULL)) {
 				vlapic->vm->wire_mode = VPIC_WIRE_LAPIC;
 				dev_dbg(ACRN_DBG_LAPIC,
 					"vpic wire mode -> LAPIC");
@@ -750,7 +750,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
 		uint32_t i, idx, vector;
 		uint32_t isrvec;
 
-		if (vlapic->isrvec_stk_top == 0U && top_isrvec != 0U) {
+		if ((vlapic->isrvec_stk_top == 0U) && (top_isrvec != 0U)) {
 			panic("isrvec_stk is corrupted: %u", top_isrvec);
 		}
 
@@ -1096,7 +1096,7 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
 	phys = ((icr_low & APIC_DESTMODE_LOG) == 0UL);
 	shorthand = icr_low & APIC_DEST_MASK;
 
-	if (mode == APIC_DELMODE_FIXED && vec < 16U) {
+	if ((mode == APIC_DELMODE_FIXED) && (vec < 16U)) {
 		vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 		dev_dbg(ACRN_DBG_LAPIC, "Ignoring invalid IPI %u", vec);
 		return 0;
@@ -1106,9 +1106,9 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
 		"icrlo 0x%08x icrhi 0x%08x triggered ipi %u",
 			icr_low, icr_high, vec);
 
-	if ((shorthand == APIC_DEST_SELF || shorthand == APIC_DEST_ALLISELF)
-		&& (mode == APIC_DELMODE_NMI || mode == APIC_DELMODE_INIT
-		|| mode == APIC_DELMODE_STARTUP)) {
+	if (((shorthand == APIC_DEST_SELF) || (shorthand == APIC_DEST_ALLISELF))
+		&& ((mode == APIC_DELMODE_NMI) || (mode == APIC_DELMODE_INIT)
+		|| (mode == APIC_DELMODE_STARTUP))) {
 		dev_dbg(ACRN_DBG_LAPIC, "Invalid ICR value");
 		return 0;
 	}
@@ -1465,7 +1465,7 @@ vlapic_write(struct acrn_vlapic *vlapic, int mmio_access, uint32_t offset,
 	uint32_t data32 = (uint32_t)data;
 	int retval;
 
-	ASSERT((offset & 0xfU) == 0U && offset < CPU_PAGE_SIZE,
+	ASSERT(((offset & 0xfU) == 0U) && (offset < CPU_PAGE_SIZE),
 		"%s: invalid offset %#x", __func__, offset);
 
 	dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#x, data %#lx",
@@ -1687,9 +1687,9 @@ vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
 	uint64_t dmask;
 	struct vcpu *target_vcpu;
 
-	if (delmode != IOAPIC_RTE_DELFIXED &&
-			delmode != IOAPIC_RTE_DELLOPRI &&
-			delmode != IOAPIC_RTE_DELEXINT) {
+	if ((delmode != IOAPIC_RTE_DELFIXED) &&
+			(delmode != IOAPIC_RTE_DELLOPRI) &&
+			(delmode != IOAPIC_RTE_DELEXINT)) {
 		dev_dbg(ACRN_DBG_LAPIC,
 			"vlapic intr invalid delmode %#x", delmode);
 		return;
@@ -1801,7 +1801,7 @@ vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
 	/*
 	 * A level trigger is valid only for fixed and lowprio delivery modes.
 	 */
-	if (delmode != APIC_DELMODE_FIXED && delmode != APIC_DELMODE_LOWPRIO) {
+	if ((delmode != APIC_DELMODE_FIXED) && (delmode != APIC_DELMODE_LOWPRIO)) {
 		dev_dbg(ACRN_DBG_LAPIC,
 			"Ignoring level trigger-mode for delivery-mode %u",
 			delmode);
@@ -1833,7 +1833,7 @@ vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
 	 * According to section "Maskable Hardware Interrupts" in Intel SDM
 	 * vectors 16 through 255 can be delivered through the local APIC.
 	 */
-	if (vector < 16U || vector > 255U) {
+	if ((vector < 16U) || (vector > 255U)) {
 		return -EINVAL;
 	}
 
@@ -1920,7 +1920,7 @@ vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
 static bool
 is_x2apic_msr(uint32_t msr)
 {
-	if (msr >= 0x800U && msr <= 0xBFFU) {
+	if ((msr >= 0x800U) && (msr <= 0xBFFU)) {
 		return true;
 	} else {
 		return false;
@@ -2036,7 +2036,7 @@ vlapic_write_mmio_reg(struct vcpu *vcpu, uint64_t gpa, uint64_t wval,
 	 * Memory mapped local apic accesses must be 4 bytes wide and
 	 * aligned on a 16-byte boundary.
 	 */
-	if (size != 4U || (off & 0xfU) != 0U) {
+	if ((size != 4U) || ((off & 0xfU) != 0U)) {
 		return -EINVAL;
 	}
 
diff --git a/hypervisor/arch/x86/guest/vmcall.c b/hypervisor/arch/x86/guest/vmcall.c
index deeb79244..12d8b2be7 100644
--- a/hypervisor/arch/x86/guest/vmcall.c
+++ b/hypervisor/arch/x86/guest/vmcall.c
@@ -28,9 +28,9 @@ int vmcall_vmexit_handler(struct vcpu *vcpu)
 		goto out;
 	}
 
-	if (!is_vm0(vm) && hypcall_id != HC_WORLD_SWITCH &&
-		hypcall_id != HC_INITIALIZE_TRUSTY &&
-		hypcall_id != HC_SAVE_RESTORE_SWORLD_CTX) {
+	if (!is_vm0(vm) && (hypcall_id != HC_WORLD_SWITCH) &&
+		(hypcall_id != HC_INITIALIZE_TRUSTY) &&
+		(hypcall_id != HC_SAVE_RESTORE_SWORLD_CTX)) {
 		pr_err("hypercall %d is only allowed from VM0!\n", hypcall_id);
 		goto out;
 	}
diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index 7fa156312..d874f944f 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -230,10 +230,10 @@ int rdmsr_vmexit_handler(struct vcpu *vcpu)
 	}
 	default:
 	{
-		if (!((msr >= MSR_IA32_MTRR_PHYSBASE_0 &&
-			msr <= MSR_IA32_MTRR_PHYSMASK_9) ||
-		      (msr >= MSR_IA32_VMX_BASIC &&
-			msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS))) {
+		if (!(((msr >= MSR_IA32_MTRR_PHYSBASE_0) &&
+			(msr <= MSR_IA32_MTRR_PHYSMASK_9)) ||
+		      ((msr >= MSR_IA32_VMX_BASIC) &&
+			(msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS)))) {
 			pr_warn("rdmsr: %lx should not come here!", msr);
 		}
 		vcpu_inject_gp(vcpu, 0U);
@@ -362,10 +362,10 @@ int wrmsr_vmexit_handler(struct vcpu *vcpu)
 	}
 	default:
 	{
-		if (!((msr >= MSR_IA32_MTRR_PHYSBASE_0 &&
-			msr <= MSR_IA32_MTRR_PHYSMASK_9) ||
-		      (msr >= MSR_IA32_VMX_BASIC &&
-			msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS))) {
+		if (!(((msr >= MSR_IA32_MTRR_PHYSBASE_0) &&
+			(msr <= MSR_IA32_MTRR_PHYSMASK_9)) ||
+		      ((msr >= MSR_IA32_VMX_BASIC) &&
+			(msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS)))) {
 			pr_warn("rdmsr: %lx should not come here!", msr);
 		}
 		vcpu_inject_gp(vcpu, 0U);
diff --git a/hypervisor/dm/vioapic.c b/hypervisor/dm/vioapic.c
index 4692094c0..119eabe5d 100644
--- a/hypervisor/dm/vioapic.c
+++ b/hypervisor/dm/vioapic.c
@@ -129,10 +129,10 @@ vioapic_set_pinstate(struct vioapic *vioapic, uint32_t pin, bool newstate)
 	}
 
 	needintr = false;
-	if (oldcnt == 0 && newcnt == 1) {
+	if ((oldcnt == 0) && (newcnt == 1)) {
 		needintr = true;
 		dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: asserted", pin);
-	} else if (oldcnt == 1 && newcnt == 0) {
+	} else if ((oldcnt == 1) && (newcnt == 0)) {
 		dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: deasserted", pin);
 	} else {
 		dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: %s, ignored, acnt %d",
@@ -337,9 +337,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 
 		changed = last.full ^ new.full;
 		/* pin0 from vpic mask/unmask */
-		if (pin == 0U && (changed & IOAPIC_RTE_INTMASK) != 0UL) {
+		if ((pin == 0U) && ((changed & IOAPIC_RTE_INTMASK) != 0UL)) {
 			/* mask -> umask */
-			if ((last.full & IOAPIC_RTE_INTMASK) != 0UL &&
+			if (((last.full & IOAPIC_RTE_INTMASK) != 0UL) &&
 				((new.full & IOAPIC_RTE_INTMASK) == 0UL)) {
 				if ((vioapic->vm->wire_mode ==
 						VPIC_WIRE_NULL) ||
@@ -355,7 +355,7 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 				}
 			/* unmask -> mask */
 			} else if (((last.full & IOAPIC_RTE_INTMASK) == 0UL) &&
-				(new.full & IOAPIC_RTE_INTMASK) != 0UL) {
+				((new.full & IOAPIC_RTE_INTMASK) != 0UL)) {
 				if (vioapic->vm->wire_mode ==
 						VPIC_WIRE_IOAPIC) {
 					vioapic->vm->wire_mode =
@@ -395,9 +395,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 		 * - previous interrupt has been EOIed
 		 * - pin level is asserted
 		 */
-		if ((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
-			IOAPIC_RTE_INTMCLR &&
-			(vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL &&
+		if (((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
+			IOAPIC_RTE_INTMCLR) &&
+			((vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL) &&
 			(vioapic->acnt[pin] > 0)) {
 			dev_dbg(ACRN_DBG_IOAPIC,
 				"ioapic pin%hhu: asserted at rtbl write, acnt %d",
@@ -410,9 +410,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 		 * remap for trigger mode change
 		 * remap for polarity change
 		 */
-		if ( (changed & IOAPIC_RTE_INTMASK) != 0UL ||
-		     (changed & IOAPIC_RTE_TRGRMOD) != 0UL ||
-		     (changed & IOAPIC_RTE_INTPOL ) != 0UL ) {
+		if ( ((changed & IOAPIC_RTE_INTMASK) != 0UL) ||
+		     ((changed & IOAPIC_RTE_TRGRMOD) != 0UL) ||
+		     ((changed & IOAPIC_RTE_INTPOL ) != 0UL) ) {
 
 			/* VM enable intr */
 			struct ptdev_intx_info intx;
@@ -472,7 +472,7 @@ vioapic_process_eoi(struct vm *vm, uint32_t vector)
 	uint32_t pin, pincount = vioapic_pincount(vm);
 	union ioapic_rte rte;
 
-	if (vector < VECTOR_DYNAMIC_START || vector > NR_MAX_VECTOR) {
+	if ((vector < VECTOR_DYNAMIC_START) || (vector > NR_MAX_VECTOR)) {
 		pr_err("vioapic_process_eoi: invalid vector %u", vector);
 	}
 
diff --git a/hypervisor/dm/vpic.c b/hypervisor/dm/vpic.c
index 10534f29a..266bd538c 100644
--- a/hypervisor/dm/vpic.c
+++ b/hypervisor/dm/vpic.c
@@ -110,7 +110,7 @@ static inline uint8_t vpic_get_highest_isrpin(struct i8259_reg_state *i8259)
 			 * An IS bit that is masked by an IMR bit will not be
 			 * cleared by a non-specific EOI in Special Mask Mode.
 			 */
-			if ((i8259->smm != 0U) && (i8259->mask & bit) != 0U) {
+			if ((i8259->smm != 0U) && ((i8259->mask & bit) != 0U)) {
 				continue;
 			} else {
 				return pin;
@@ -160,7 +160,7 @@ static inline uint8_t vpic_get_highest_irrpin(struct i8259_reg_state *i8259)
 		 * If an interrupt is asserted and not masked then return
 		 * the corresponding 'pin' to the caller.
 		 */
-		if ((i8259->request & bit) != 0 && (i8259->mask & bit) == 0) {
+		if (((i8259->request & bit) != 0) && ((i8259->mask & bit) == 0)) {
 			return pin;
 		}
 	}
@@ -178,7 +178,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
 	 */
 	i8259 = &vpic->i8259[1];
 	pin = vpic_get_highest_irrpin(i8259);
-	if (!i8259->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
+	if (!i8259->intr_raised && (pin < NR_VPIC_PINS_PER_CHIP)) {
 		dev_dbg(ACRN_DBG_PIC,
 		"pic slave notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
 		pin, i8259->mask, i8259->request, i8259->service);
@@ -200,7 +200,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
 	 */
 	i8259 = &vpic->i8259[0];
 	pin = vpic_get_highest_irrpin(i8259);
-	if (!i8259->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
+	if (!i8259->intr_raised && (pin < NR_VPIC_PINS_PER_CHIP)) {
 		dev_dbg(ACRN_DBG_PIC,
 		"pic master notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
 		pin, i8259->mask, i8259->request, i8259->service);
@@ -427,7 +427,7 @@ static int vpic_ocw2(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint
 				(master_pic(vpic, i8259) ? isr_bit : isr_bit + 8U),
 				PTDEV_VPIN_PIC);
 		}
-	} else if ((val & OCW2_SL) != 0U && i8259->rotate) {
+	} else if (((val & OCW2_SL) != 0U) && i8259->rotate) {
 		/* specific priority */
 		i8259->lowprio = val & 0x7U;
 	} else {
@@ -485,11 +485,11 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, bool newstate
 
 	level = ((vpic->i8259[pin >> 3U].elc & (1U << (pin & 0x7U))) != 0);
 
-	if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
+	if (((oldcnt == 0) && (newcnt == 1)) || ((newcnt > 0) && (level == true))) {
 		/* rising edge or level */
 		dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: asserted\n", pin);
 		i8259->request |= (uint8_t)(1U << (pin & 0x7U));
-	} else if (oldcnt == 1 && newcnt == 0) {
+	} else if ((oldcnt == 1) && (newcnt == 0)) {
 		/* falling edge */
 		dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: deasserted\n", pin);
 		if (level) {