From 6fd397e82b6bfce5060c3758e7429920ff27a4d6 Mon Sep 17 00:00:00 2001 From: Yuan Liu Date: Thu, 13 Jun 2019 17:40:05 +0800 Subject: [PATCH] HV: Add CLFLUSHOPT instruction. CLFLUSHOPT is used to invalidate from every level of the cache hierarchy in the cache coherence domain the cache line that contains the linear address specified with memory operand. If that cache line contains modified date at any level of the cache hierarchy, that data is written back to memory. If the platform does not support CLFLUSHOPT instruction, boot will fail. Signed-off-by: Jack Ren Signed-off-by: Yuan Liu Reviewed-by: Li, Fei1 Acked-by: Eddie Dong --- hypervisor/arch/x86/cpu_caps.c | 3 +++ hypervisor/include/arch/x86/cpufeatures.h | 1 + hypervisor/include/arch/x86/mmu.h | 5 +++++ 3 files changed, 9 insertions(+) diff --git a/hypervisor/arch/x86/cpu_caps.c b/hypervisor/arch/x86/cpu_caps.c index d8226939d..1c07e326e 100644 --- a/hypervisor/arch/x86/cpu_caps.c +++ b/hypervisor/arch/x86/cpu_caps.c @@ -386,6 +386,9 @@ int32_t detect_hardware_support(void) } else if (!pcpu_has_cap(X86_FEATURE_MTRR)) { pr_fatal("%s, MTRR not supported\n", __func__); ret = -ENODEV; + } else if (!pcpu_has_cap(X86_FEATURE_CLFLUSHOPT)) { + pr_fatal("%s, CLFLUSHOPT not supported\n", __func__); + ret = -ENODEV; } else if (!pcpu_has_cap(X86_FEATURE_PAGE1GB)) { pr_fatal("%s, not support 1GB page\n", __func__); ret = -ENODEV; diff --git a/hypervisor/include/arch/x86/cpufeatures.h b/hypervisor/include/arch/x86/cpufeatures.h index b49205221..bbf83a596 100644 --- a/hypervisor/include/arch/x86/cpufeatures.h +++ b/hypervisor/include/arch/x86/cpufeatures.h @@ -76,6 +76,7 @@ #define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U) #define X86_FEATURE_CAT ((FEAT_7_0_EBX << 5U) + 15U) #define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U) +#define X86_FEATURE_CLFLUSHOPT ((FEAT_7_0_EBX << 5U) + 23U) /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/ #define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U) diff --git a/hypervisor/include/arch/x86/mmu.h b/hypervisor/include/arch/x86/mmu.h index bc760f293..b6b7790b3 100644 --- a/hypervisor/include/arch/x86/mmu.h +++ b/hypervisor/include/arch/x86/mmu.h @@ -169,6 +169,11 @@ static inline void clflush(volatile void *p) asm volatile ("clflush (%0)" :: "r"(p)); } +static inline void clflushopt(volatile void *p) +{ + asm volatile ("clflushopt (%0)" :: "r"(p)); +} + /* get PDPT address from CR3 vaule in PAE mode */ static inline uint64_t get_pae_pdpt_addr(uint64_t cr3) {