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hv: vmsr: refine x2apic MSR bitmap setting

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In theory, we should trap out all the x2apic MSR access if APICv is not enabled.
When "Use TPR shadow" and "Virtualize x2APIC mode" are enabled, we could disable
TPR interception; when APICv is fully enabled, besides TPR, we could disable all
MSR read, EOI and self-IPI interception; when we pass through lapic to guest, we
could disable all the MSR access interception except XAPICID/LDR read and ICR write.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
This commit is contained in:
Li, Fei1
2019-03-21 07:43:23 +08:00
committed by wenlingz
parent 0c347e607a
commit 70dd254456
3 changed files with 26 additions and 113 deletions
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6
hypervisor/include/arch/x86/msr.h
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@@ -561,14 +561,10 @@ static inline bool pat_mem_type_invalid(uint64_t x)
static inline bool is_x2apic_msr(uint32_t msr)
{
bool ret = false;
/*
* if msr is in the range of x2APIC MSRs
*/
if ((msr >= MSR_IA32_EXT_XAPICID) && (msr <= MSR_IA32_EXT_APIC_SELF_IPI)) {
ret = true;
}
return ret;
return ((msr >= 0x800U) && (msr < 0x900U));
}
static inline bool is_x2apic_read_only_msr(uint32_t msr)