hv: ptct: init psram on all cores

Call PTCM command interface to initialize pSRAM on all CPU cores.
Becuase HV need to call PTCM command interface which is not a HV code text,
now we WA to remove the NX for HV.

Tracked-On: #5330

Signed-off-by: Qian Wang <qian1.wang@intel.com>
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>

hypervisor/arch/x86/cpu.c

@@ -28,6 +28,7 @@
 #include <sgx.h>
 #include <uart16550.h>
 #include <ivshmem.h>
+#include <ptct.h>
 
 #define CPU_UP_TIMEOUT		100U /* millisecond */
 #define CPU_DOWN_TIMEOUT	100U /* millisecond */
@@ -267,11 +268,15 @@ void init_pcpu_post(uint16_t pcpu_id)
 		}
 
 		ASSERT(get_pcpu_id() == BSP_CPU_ID, "");
+
+		init_psram(true);
 	} else {
 		pr_dbg("Core %hu is up", pcpu_id);
 
 		pr_warn("Skipping VM configuration check which should be done before building HV binary.");
 
+		init_psram(false);
+
 		/* Initialize secondary processor interrupts. */
 		init_interrupt(pcpu_id);
 

hypervisor/arch/x86/mmu.c

@@ -216,7 +216,9 @@ void init_paging(void)
 	uint32_t i;
 	uint64_t low32_max_ram = 0UL;
 	uint64_t high64_max_ram;
-	uint64_t attr_uc = (PAGE_PRESENT | PAGE_RW | PAGE_USER | PAGE_CACHE_UC | PAGE_NX);
+	//uint64_t attr_uc = (PAGE_PRESENT | PAGE_RW | PAGE_USER | PAGE_CACHE_UC | PAGE_NX);
+	/* FIXME: use IA32_EFER.NXE to fix this issue */
+	uint64_t attr_uc = (PAGE_PRESENT | PAGE_RW | PAGE_USER | PAGE_CACHE_UC);
 
 	const struct e820_entry *entry;
 	uint32_t entries_count = get_e820_entries_count();

hypervisor/arch/x86/ptcm.c

@@ -6,7 +6,7 @@
 #include <types.h>
 #include <logmsg.h>
 #include <misc_cfg.h>
-#include <ptct.h>
+#include <ptcm.h>
 
 uint64_t psram_area_bottom = PSRAM_BASE_HPA;
 uint64_t psram_area_top = PSRAM_BASE_HPA;
@@ -99,4 +99,55 @@ static void parse_ptct(void)
 	}
 }
 
+static volatile uint64_t ptcm_command_interface_offset;
+static volatile struct ptct_entry* ptct_base_entry;
+static volatile ptcm_command_abi ptcm_command_interface = NULL;
+static volatile bool psram_is_initialized = false;
+
+void init_psram(bool is_bsp)
+{
+	uint32_t magic,version;
+	int ret;
+
+	if (is_bsp) {
+		parse_ptct();
+		pr_fatal("PTCT is parsed by BSP");
+		ptct_base_entry = (struct ptct_entry*)((uint64_t)get_acpi_tbl(ACPI_SIG_PTCT) + 0x24);
+		pr_fatal("ptct_base_entry is found by BSP at %llx", ptct_base_entry);
+		magic = ((uint32_t *)ptcm_binary.address)[0];
+		version = ((uint32_t *)ptcm_binary.address)[1];
+		ptcm_command_interface_offset =*(uint64_t *)(ptcm_binary.address + 0x8);
+		pr_fatal("ptcm_bin_address:%llx", ptcm_binary.address);
+		pr_fatal("ptcm_command_interface_offset is %llx", ptcm_command_interface_offset);
+		pr_fatal("magic:%x", magic);
+		pr_fatal("version:%x", version);
+
+		ptcm_command_interface = (ptcm_command_abi)(ptcm_binary.address + ptcm_command_interface_offset);
+		pr_fatal("ptcm_command_interface is found at %llx",ptcm_command_interface);
+	} else {
+		//all AP should wait until BSP finishes parsing PTCT and finding the command interface.
+		while (!ptcm_command_interface) {
+			continue;
+		}
+	}
+
+	ret = ptcm_command_interface(PTCM_CMD_INIT_PSRAM, (void *)ptct_base_entry);
+	pr_fatal("PTCM initialization for core %d with return code %d!!!!!!!!!!!!!", get_pcpu_id(), ret);
+	/* TODO: to handle the return errno gracefully */
+	ASSERT(ret == PTCM_STATUS_SUCCESS);
+
+	/* wait until all cores finishes pSRAM initialization*/
+	if (is_bsp){
+		psram_is_initialized = true;
+		pr_fatal("BSP pSRAM has been initialized\n");
+	} else{
+		while (psram_is_initialized) {
+			continue;
+		}
+	}
+}
+#else
+void init_psram(__unused bool is_bsp)
+{
+}
 #endif

hypervisor/include/arch/x86/ptcm.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PTCM_H
+#define PTCM_H
+
+#include <ptct.h>
+
+#define MSABI __attribute__((ms_abi))
+
+typedef int32_t MSABI (*ptcm_command_abi)(uint32_t command, void *command_struct);
+
+#define PTCM_CMD_INIT_PSRAM (int32_t)1U
+#define PTCM_CMD_CPUID (int32_t)2U
+#define PTCM_CMD_RDMSR (int32_t)3U
+#define PTCM_CMD_WRMSR (int32_t)4U
+
+#define PCTM_L2_CLOS_MASK_MAX_NUM 8U
+#define PCTM_L3_CLOS_MASK_MAX_NUM 4U
+
+#define PTCM_STATUS_SUCCESS 0
+#define PTCM_STATUS_FAILURE -1
+
+struct ptcm_info
+{
+    uint32_t version;           // [OUT]
+    uint32_t max_command_index; // [OUT]
+};
+
+struct ptcm_header
+{
+    uint32_t magic;
+    uint32_t version;
+    uint64_t command_interface_offset;
+};
+
+#endif /* PTCM_H */

hypervisor/include/arch/x86/ptct.h

@@ -101,4 +101,5 @@ struct ptcm_mem_region
 
 extern uint64_t psram_area_bottom;
 extern uint64_t psram_area_top;
+void init_psram(bool is_bsp);
 #endif	/* PTCT_H */