mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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modulization: separate vmx.c into two parts
one part is pure vmx operations which keeps in vmx.c the other part is vmcs operations which is vcpu related, move them into vmcs.c Changes to be committed: modified: Makefile copied: arch/x86/vmx.c -> arch/x86/vmcs.c modified: arch/x86/vmx.c modified: arch/x86/vmx_asm.S modified: include/arch/x86/hv_arch.h new file: include/arch/x86/vmcs.h modified: include/arch/x86/vmx.h Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ
wenlingz
@@ -34,6 +34,7 @@
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#include <pgtable.h>
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#include <irq.h>
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#include <vmx.h>
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#include <vmcs.h>
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#include <assign.h>
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#include <vtd.h>
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85
hypervisor/include/arch/x86/vmcs.h
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85
hypervisor/include/arch/x86/vmcs.h
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@@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VMCS_H_
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#define VMCS_H_
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#define VM_SUCCESS 0
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#define VM_FAIL -1
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#define VMX_VMENTRY_FAIL 0x80000000U
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#ifndef ASSEMBLER
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static inline uint32_t vmx_eoi_exit(uint32_t vector)
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{
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return (VMX_EOI_EXIT0_FULL + ((vector >> 6U) * 2U));
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}
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/* VM exit qulifications for APIC-access
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* Access type:
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* 0 = linear access for a data read during instruction execution
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* 1 = linear access for a data write during instruction execution
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* 2 = linear access for an instruction fetch
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* 3 = linear access (read or write) during event delivery
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* 10 = guest-physical access during event delivery
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* 15 = guest-physical access for an instructon fetch or during
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* instruction execution
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*/
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static inline uint64_t apic_access_type(uint64_t qual)
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{
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return ((qual >> 12U) & 0xFUL);
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}
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static inline uint64_t apic_access_offset(uint64_t qual)
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{
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return (qual & 0xFFFUL);
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}
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#define RFLAGS_C (1U<<0U)
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#define RFLAGS_Z (1U<<6U)
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#define RFLAGS_AC (1U<<18U)
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/* CR0 bits hv want to trap to track status change */
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#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP | CR0_CD | CR0_NW )
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#define CR0_RESERVED_MASK ~(CR0_PG | CR0_CD | CR0_NW | CR0_AM | CR0_WP | \
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CR0_NE | CR0_ET | CR0_TS | CR0_EM | CR0_MP | CR0_PE)
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/* CR4 bits hv want to trap to track status change */
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#define CR4_TRAP_MASK (CR4_PSE | CR4_PAE | CR4_VMXE | CR4_PCIDE)
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#define CR4_RESERVED_MASK ~(CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | \
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CR4_PAE | CR4_MCE | CR4_PGE | CR4_PCE | \
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CR4_OSFXSR | CR4_PCIDE | CR4_OSXSAVE | \
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CR4_SMEP | CR4_FSGSBASE | CR4_VMXE | \
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CR4_OSXMMEXCPT | CR4_SMAP | CR4_PKE | \
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CR4_SMXE | CR4_UMIP )
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#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5U)
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void init_vmcs(struct acrn_vcpu *vcpu);
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uint64_t vmx_rdmsr_pat(const struct acrn_vcpu *vcpu);
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int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value);
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void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0);
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void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4);
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bool is_vmx_disabled(void);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
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{
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return vcpu->arch.cpu_mode;
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}
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static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
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{
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return ((msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST)
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!= 0UL);
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}
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#endif /* ASSEMBLER */
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#endif /* VMCS_H_ */
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@@ -377,61 +377,11 @@
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#define VMX_INT_TYPE_HW_EXP 3U
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#define VMX_INT_TYPE_SW_EXP 6U
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#define VM_SUCCESS 0
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#define VM_FAIL -1
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#define VMX_VMENTRY_FAIL 0x80000000U
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#ifndef ASSEMBLER
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static inline uint32_t vmx_eoi_exit(uint32_t vector)
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{
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return (VMX_EOI_EXIT0_FULL + ((vector >> 6U) * 2U));
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}
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/* VM exit qulifications for APIC-access
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* Access type:
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* 0 = linear access for a data read during instruction execution
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* 1 = linear access for a data write during instruction execution
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* 2 = linear access for an instruction fetch
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* 3 = linear access (read or write) during event delivery
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* 10 = guest-physical access during event delivery
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* 15 = guest-physical access for an instructon fetch or during
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* instruction execution
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*/
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static inline uint64_t apic_access_type(uint64_t qual)
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{
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return ((qual >> 12U) & 0xFUL);
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}
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static inline uint64_t apic_access_offset(uint64_t qual)
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{
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return (qual & 0xFFFUL);
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}
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#define RFLAGS_C (1U<<0U)
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#define RFLAGS_Z (1U<<6U)
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#define RFLAGS_AC (1U<<18U)
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/* CR0 bits hv want to trap to track status change */
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#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP | CR0_CD | CR0_NW )
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#define CR0_RESERVED_MASK ~(CR0_PG | CR0_CD | CR0_NW | CR0_AM | CR0_WP | \
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CR0_NE | CR0_ET | CR0_TS | CR0_EM | CR0_MP | CR0_PE)
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/* CR4 bits hv want to trap to track status change */
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#define CR4_TRAP_MASK (CR4_PSE | CR4_PAE | CR4_VMXE | CR4_PCIDE)
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#define CR4_RESERVED_MASK ~(CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | \
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CR4_PAE | CR4_MCE | CR4_PGE | CR4_PCE | \
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CR4_OSFXSR | CR4_PCIDE | CR4_OSXSAVE | \
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CR4_SMEP | CR4_FSGSBASE | CR4_VMXE | \
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CR4_OSXMMEXCPT | CR4_SMAP | CR4_PKE | \
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CR4_SMXE | CR4_UMIP )
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#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5U)
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/* External Interfaces */
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void exec_vmxon_instr(uint16_t pcpu_id);
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void vmx_off(uint16_t pcpu_id);
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/**
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* Read field from VMCS.
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*
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@@ -451,32 +401,7 @@ void exec_vmwrite32(uint32_t field, uint32_t value);
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void exec_vmwrite64(uint32_t field_full, uint64_t value);
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#define exec_vmwrite exec_vmwrite64
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void init_vmcs(struct acrn_vcpu *vcpu);
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void vmx_off(uint16_t pcpu_id);
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void exec_vmclear(void *addr);
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void exec_vmptrld(void *addr);
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uint64_t vmx_rdmsr_pat(const struct acrn_vcpu *vcpu);
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int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value);
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void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0);
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void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4);
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bool is_vmx_disabled(void);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
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{
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return vcpu->arch.cpu_mode;
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}
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static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
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{
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return ((msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST)
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!= 0UL);
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}
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#endif /* ASSEMBLER */
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#endif /* VMX_H_ */
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