diff --git a/hypervisor/arch/x86/ioapic.c b/hypervisor/arch/x86/ioapic.c index 8e0f89d42..af87a15ef 100644 --- a/hypervisor/arch/x86/ioapic.c +++ b/hypervisor/arch/x86/ioapic.c @@ -17,6 +17,27 @@ #define NR_MAX_GSI (CONFIG_MAX_IOAPIC_NUM * CONFIG_MAX_IOAPIC_LINES) +#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTMODE_LOGICAL +#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELMODE_LOPRI + +/* + * is_valid is by default false when all the + * static variables, part of .bss, are initialized to 0s + * It is set to true, if the corresponding + * gsi falls in ranges identified by IOAPIC data + * in ACPI MADT in ioapic_setup_irqs. + */ + +struct gsi_table { + bool is_valid; + struct { + uint8_t acpi_id; + uint8_t index; + uint32_t pin; + void *base_addr; + } ioapic_info; +}; + static struct gsi_table gsi_table_data[NR_MAX_GSI]; static uint32_t ioapic_max_nr_gsi; static spinlock_t ioapic_lock = { .head = 0U, .tail = 0U, }; diff --git a/hypervisor/arch/x86/lapic.c b/hypervisor/arch/x86/lapic.c index 2ff017ea6..6f0f70c34 100644 --- a/hypervisor/arch/x86/lapic.c +++ b/hypervisor/arch/x86/lapic.c @@ -11,6 +11,33 @@ #include #include #include +#include + +/* intr_lapic_icr_delivery_mode */ +#define INTR_LAPIC_ICR_FIXED 0x0U +#define INTR_LAPIC_ICR_LP 0x1U +#define INTR_LAPIC_ICR_SMI 0x2U +#define INTR_LAPIC_ICR_NMI 0x4U +#define INTR_LAPIC_ICR_INIT 0x5U +#define INTR_LAPIC_ICR_STARTUP 0x6U + +/* intr_lapic_icr_dest_mode */ +#define INTR_LAPIC_ICR_PHYSICAL 0x0U +#define INTR_LAPIC_ICR_LOGICAL 0x1U + +/* intr_lapic_icr_level */ +#define INTR_LAPIC_ICR_DEASSERT 0x0U +#define INTR_LAPIC_ICR_ASSERT 0x1U + +/* intr_lapic_icr_trigger */ +#define INTR_LAPIC_ICR_EDGE 0x0U +#define INTR_LAPIC_ICR_LEVEL 0x1U + +/* intr_lapic_icr_shorthand */ +#define INTR_LAPIC_ICR_USE_DEST_ARRAY 0x0U +#define INTR_LAPIC_ICR_SELF 0x1U +#define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U +#define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U union lapic_base_msr { uint64_t value; @@ -87,7 +114,7 @@ void init_lapic(uint16_t pcpu_id) clear_lapic_isr(); } -void save_lapic(struct lapic_regs *regs) +static void save_lapic(struct lapic_regs *regs) { regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR); regs->ppr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_PPR); diff --git a/hypervisor/include/arch/x86/ioapic.h b/hypervisor/include/arch/x86/ioapic.h index a96ccaa70..9ac65af82 100644 --- a/hypervisor/include/arch/x86/ioapic.h +++ b/hypervisor/include/arch/x86/ioapic.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef IOAPIC_H -#define IOAPIC_H +#ifndef ARCH_X86_IOAPIC_H +#define ARCH_X86_IOAPIC_H #include @@ -90,27 +90,10 @@ void ioapic_gsi_unmask_irq(uint32_t irq); void ioapic_get_rte_entry(void *ioapic_base, uint32_t pin, union ioapic_rte *rte); -/* - * is_valid is by default false when all the - * static variables, part of .bss, are initialized to 0s - * It is set to true, if the corresponding - * gsi falls in ranges identified by IOAPIC data - * in ACPI MADT in ioapic_setup_irqs. - */ - -struct gsi_table { - bool is_valid; - struct { - uint8_t acpi_id; - uint8_t index; - uint32_t pin; - void *base_addr; - } ioapic_info; -}; - void *gsi_to_ioapic_base(uint32_t gsi); uint32_t get_max_nr_gsi(void); uint8_t get_gsi_to_ioapic_index(uint32_t gsi); uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index); bool is_gsi_valid(uint32_t gsi); -#endif /* IOAPIC_H */ + +#endif /* ARCH_X86_IOAPIC_H */ diff --git a/hypervisor/include/arch/x86/irq.h b/hypervisor/include/arch/x86/irq.h index bce1a0cdc..da6287aac 100644 --- a/hypervisor/include/arch/x86/irq.h +++ b/hypervisor/include/arch/x86/irq.h @@ -77,9 +77,6 @@ */ #define MAX_MSI_ENTRY 0x800U -#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTMODE_LOGICAL -#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELMODE_LOPRI - #define INVALID_INTERRUPT_PIN 0xffffffffU /* diff --git a/hypervisor/include/arch/x86/lapic.h b/hypervisor/include/arch/x86/lapic.h index 5d4ed845a..1e78daf97 100644 --- a/hypervisor/include/arch/x86/lapic.h +++ b/hypervisor/include/arch/x86/lapic.h @@ -4,43 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef INTR_LAPIC_H -#define INTR_LAPIC_H +#ifndef ARCH_X86_LAPIC_H +#define ARCH_X86_LAPIC_H #include -#include - -/* intr_lapic_icr_delivery_mode */ -#define INTR_LAPIC_ICR_FIXED 0x0U -#define INTR_LAPIC_ICR_LP 0x1U -#define INTR_LAPIC_ICR_SMI 0x2U -#define INTR_LAPIC_ICR_NMI 0x4U -#define INTR_LAPIC_ICR_INIT 0x5U -#define INTR_LAPIC_ICR_STARTUP 0x6U - -/* intr_lapic_icr_dest_mode */ -#define INTR_LAPIC_ICR_PHYSICAL 0x0U -#define INTR_LAPIC_ICR_LOGICAL 0x1U - -/* intr_lapic_icr_level */ -#define INTR_LAPIC_ICR_DEASSERT 0x0U -#define INTR_LAPIC_ICR_ASSERT 0x1U - -/* intr_lapic_icr_trigger */ -#define INTR_LAPIC_ICR_EDGE 0x0U -#define INTR_LAPIC_ICR_LEVEL 0x1U - -/* intr_lapic_icr_shorthand */ -#define INTR_LAPIC_ICR_USE_DEST_ARRAY 0x0U -#define INTR_LAPIC_ICR_SELF 0x1U -#define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U -#define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U - -enum intr_cpu_startup_shorthand { - INTR_CPU_STARTUP_USE_DEST, - INTR_CPU_STARTUP_ALL_EX_SELF, - INTR_CPU_STARTUP_UNKNOWN, -}; /* x2APIC Interrupt Command Register (ICR) structure */ union apic_icr { @@ -71,14 +38,6 @@ union apic_icr { * @{ */ -/** - * @brief Save context of LAPIC - * - * @param[inout] regs Pointer to struct lapic_regs to hold the - * context of current LAPIC - */ -void save_lapic(struct lapic_regs *regs); - /** * @brief Enable LAPIC in x2APIC mode * @@ -167,4 +126,4 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector); */ void send_single_nmi(uint16_t pcpu_id); -#endif /* INTR_LAPIC_H */ +#endif /* ARCH_X86_LAPIC_H */