mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-09-05 02:40:37 +00:00
modulization: move functions related with cpu caps into cpu_caps.c
move cpu caps related functions like capability init/detect/check in cpu.c & mmu.c into a new file cpu_caps.c Changes to be committed: modified: developer-guides/hld/hv-memmgt.rst modified: ../hypervisor/Makefile modified: ../hypervisor/arch/x86/cpu.c new file: ../hypervisor/arch/x86/cpu_caps.c modified: ../hypervisor/arch/x86/mmu.c modified: ../hypervisor/arch/x86/vmx_asm.S modified: ../hypervisor/include/arch/x86/cpu.h new file: ../hypervisor/include/arch/x86/cpu_caps.h modified: ../hypervisor/include/arch/x86/guest/vm.h modified: ../hypervisor/include/arch/x86/mmu.h modified: ../hypervisor/include/arch/x86/vmcs.h Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Jason Chen CJ
wenlingz
@@ -127,15 +127,6 @@
|
||||
/* Boot CPU ID */
|
||||
#define BOOT_CPU_ID 0U
|
||||
|
||||
/* type of speculation control
|
||||
* 0 - no speculation control support
|
||||
* 1 - raw IBRS + IPBP support
|
||||
* 2 - with STIBP optimization support
|
||||
*/
|
||||
#define IBRS_NONE 0
|
||||
#define IBRS_RAW 1
|
||||
#define IBRS_OPT 2
|
||||
|
||||
#ifndef ASSEMBLER
|
||||
|
||||
#define BUS_LOCK "lock ; "
|
||||
@@ -209,8 +200,6 @@ extern uint8_t ld_bss_end;
|
||||
extern uint64_t main_entry[1];
|
||||
extern uint64_t secondary_cpu_stack[1];
|
||||
|
||||
extern int32_t ibrs_type;
|
||||
|
||||
/*
|
||||
* To support per_cpu access, we use a special struct "per_cpu_region" to hold
|
||||
* the pattern of per CPU data. And we allocate memory for per CPU data
|
||||
@@ -229,16 +218,6 @@ extern int32_t ibrs_type;
|
||||
* to locate the per cpu data.
|
||||
*/
|
||||
|
||||
/* CPUID feature words */
|
||||
#define FEAT_1_ECX 0U /* CPUID[1].ECX */
|
||||
#define FEAT_1_EDX 1U /* CPUID[1].EDX */
|
||||
#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */
|
||||
#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */
|
||||
#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
|
||||
#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
|
||||
#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
|
||||
#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */
|
||||
#define FEATURE_WORDS 8U
|
||||
/**
|
||||
*The invalid cpu_id (INVALID_CPU_ID) is error
|
||||
*code for error handling, this means that
|
||||
@@ -267,24 +246,6 @@ enum pcpu_boot_state {
|
||||
PCPU_STATE_DEAD,
|
||||
};
|
||||
|
||||
struct cpu_state_info {
|
||||
uint8_t px_cnt; /* count of all Px states */
|
||||
const struct cpu_px_data *px_data;
|
||||
uint8_t cx_cnt; /* count of all Cx entries */
|
||||
const struct cpu_cx_data *cx_data;
|
||||
};
|
||||
|
||||
struct cpuinfo_x86 {
|
||||
uint8_t family, model;
|
||||
uint8_t virt_bits;
|
||||
uint8_t phys_bits;
|
||||
uint32_t cpuid_level;
|
||||
uint32_t extended_cpuid_level;
|
||||
uint64_t physical_address_mask;
|
||||
uint32_t cpuid_leaves[FEATURE_WORDS];
|
||||
char model_name[64];
|
||||
struct cpu_state_info state_info;
|
||||
};
|
||||
#ifdef STACK_PROTECTOR
|
||||
struct stack_canary {
|
||||
/* Gcc generates extra code, using [fs:40] to access canary */
|
||||
@@ -294,32 +255,16 @@ struct stack_canary {
|
||||
void __stack_chk_fail(void);
|
||||
#endif
|
||||
|
||||
extern struct cpuinfo_x86 boot_cpu_data;
|
||||
|
||||
#define MAX_PSTATE 20U /* max num of supported Px count */
|
||||
#define MAX_CSTATE 8U /* max num of supported Cx count */
|
||||
|
||||
/* We support MAX_CSTATE num of Cx, means have (MAX_CSTATE - 1) Cx entries,
|
||||
* i.e. supported Cx entry index range from 1 to MAX_CX_ENTRY.
|
||||
*/
|
||||
#define MAX_CX_ENTRY (MAX_CSTATE - 1U)
|
||||
|
||||
/* Function prototypes */
|
||||
void cpu_do_idle(void);
|
||||
void cpu_dead(void);
|
||||
void trampoline_start16(void);
|
||||
bool is_apicv_reg_virtualization_supported(void);
|
||||
bool is_apicv_intr_delivery_supported(void);
|
||||
bool is_apicv_posted_intr_supported(void);
|
||||
bool is_ept_supported(void);
|
||||
bool cpu_has_cap(uint32_t bit);
|
||||
void load_cpu_state_data(void);
|
||||
void init_cpu_pre(uint16_t pcpu_id);
|
||||
void init_cpu_post(uint16_t pcpu_id);
|
||||
void start_cpus(void);
|
||||
void stop_cpus(void);
|
||||
void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
|
||||
void cpu_l1d_flush(void);
|
||||
|
||||
#define CPU_SEG_READ(seg, result_ptr) \
|
||||
{ \
|
||||
|
||||
79
hypervisor/include/arch/x86/cpu_caps.h
Normal file
79
hypervisor/include/arch/x86/cpu_caps.h
Normal file
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CPUINFO_H
|
||||
#define CPUINFO_H
|
||||
|
||||
/* type of speculation control
|
||||
* 0 - no speculation control support
|
||||
* 1 - raw IBRS + IPBP support
|
||||
* 2 - with STIBP optimization support
|
||||
*/
|
||||
#define IBRS_NONE 0
|
||||
#define IBRS_RAW 1
|
||||
#define IBRS_OPT 2
|
||||
|
||||
#ifndef ASSEMBLER
|
||||
|
||||
extern int32_t ibrs_type;
|
||||
|
||||
struct cpu_state_info {
|
||||
uint8_t px_cnt; /* count of all Px states */
|
||||
const struct cpu_px_data *px_data;
|
||||
uint8_t cx_cnt; /* count of all Cx entries */
|
||||
const struct cpu_cx_data *cx_data;
|
||||
};
|
||||
|
||||
#define MAX_PSTATE 20U /* max num of supported Px count */
|
||||
#define MAX_CSTATE 8U /* max num of supported Cx count */
|
||||
/* We support MAX_CSTATE num of Cx, means have (MAX_CSTATE - 1) Cx entries,
|
||||
* i.e. supported Cx entry index range from 1 to MAX_CX_ENTRY.
|
||||
*/
|
||||
#define MAX_CX_ENTRY (MAX_CSTATE - 1U)
|
||||
|
||||
/* CPUID feature words */
|
||||
#define FEAT_1_ECX 0U /* CPUID[1].ECX */
|
||||
#define FEAT_1_EDX 1U /* CPUID[1].EDX */
|
||||
#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */
|
||||
#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */
|
||||
#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
|
||||
#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
|
||||
#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
|
||||
#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */
|
||||
#define FEATURE_WORDS 8U
|
||||
|
||||
struct cpuinfo_x86 {
|
||||
uint8_t family, model;
|
||||
uint8_t virt_bits;
|
||||
uint8_t phys_bits;
|
||||
uint32_t cpuid_level;
|
||||
uint32_t extended_cpuid_level;
|
||||
uint64_t physical_address_mask;
|
||||
uint32_t cpuid_leaves[FEATURE_WORDS];
|
||||
char model_name[64];
|
||||
struct cpu_state_info state_info;
|
||||
};
|
||||
|
||||
extern struct cpuinfo_x86 boot_cpu_data;
|
||||
|
||||
bool get_monitor_cap(void);
|
||||
bool is_apicv_reg_virtualization_supported(void);
|
||||
bool is_apicv_intr_delivery_supported(void);
|
||||
bool is_apicv_posted_intr_supported(void);
|
||||
bool is_ept_supported(void);
|
||||
bool cpu_has_cap(uint32_t bit);
|
||||
bool cpu_has_vmx_ept_cap(uint32_t bit_mask);
|
||||
bool cpu_has_vmx_vpid_cap(uint32_t bit_mask);
|
||||
void get_cpu_capabilities(void);
|
||||
void get_cpu_name(void);
|
||||
void cpu_cap_detect(void);
|
||||
bool check_cpu_security_config(void);
|
||||
void cpu_l1d_flush(void);
|
||||
int hardware_detect_support(void);
|
||||
|
||||
#endif /* ASSEMBLER */
|
||||
|
||||
#endif /* CPUINFO_H */
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <bsp_extern.h>
|
||||
#include <vpci.h>
|
||||
#include <page.h>
|
||||
#include <cpu_caps.h>
|
||||
|
||||
#ifdef CONFIG_PARTITION_MODE
|
||||
#include <mptable.h>
|
||||
|
||||
@@ -126,13 +126,6 @@ void mmu_modify_or_del(uint64_t *pml4_page, uint64_t vaddr_base, uint64_t size,
|
||||
uint64_t prot_set, uint64_t prot_clr, const struct memory_ops *mem_ops, uint32_t type);
|
||||
void hv_access_memory_region_update(uint64_t base, uint64_t size);
|
||||
|
||||
/**
|
||||
* @brief EPT and VPID capability checking
|
||||
*
|
||||
* @retval 0 on success
|
||||
* @retval -ENODEV Don't support EPT or VPID capability
|
||||
*/
|
||||
int32_t check_vmx_mmu_cap(void);
|
||||
/**
|
||||
* @brief VPID allocation
|
||||
*
|
||||
|
||||
@@ -66,7 +66,6 @@ int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value);
|
||||
|
||||
void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0);
|
||||
void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4);
|
||||
bool is_vmx_disabled(void);
|
||||
void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
|
||||
|
||||
static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
|
||||
@@ -74,12 +73,6 @@ static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
|
||||
return vcpu->arch.cpu_mode;
|
||||
}
|
||||
|
||||
static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
|
||||
{
|
||||
return ((msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST)
|
||||
!= 0UL);
|
||||
}
|
||||
|
||||
#endif /* ASSEMBLER */
|
||||
|
||||
#endif /* VMCS_H_ */
|
||||
|
||||
Reference in New Issue
Block a user