hv: multi-arch reconstruct memory library

Split common and X86 arch specific codes.
For arch without specific memory library,add common library
to use.

Tracked-On: #8794
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Co-developed-by: Haoyu Tang <haoyu.tang@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Signed-off-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Haicheng Li
2025-09-07 15:26:43 +08:00
committed by acrnsi-robot
parent a93e9a401c
commit 7573e436a5
8 changed files with 153 additions and 55 deletions

View File

@@ -149,6 +149,7 @@ endif
# all the work. # all the work.
# #
COMMON_C_SRCS += common/notify.c COMMON_C_SRCS += common/notify.c
COMMON_C_SRCS += lib/memory.c
ifeq ($(ARCH),x86) ifeq ($(ARCH),x86)
COMMON_C_SRCS += common/ticks.c COMMON_C_SRCS += common/ticks.c

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@@ -1,30 +1,18 @@
/* /*
* Copyright (C) 2018-2022 Intel Corporation. * Copyright (C) 2018-2025 Intel Corporation.
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <types.h> #include <types.h>
#include <memory.h>
static inline void memset_erms(void *base, uint8_t v, size_t n) static inline void x86_memset(void *base, uint8_t v, size_t n)
{ {
asm volatile("rep ; stosb" asm volatile("rep ; stosb"
: "+D"(base) : "+D"(base)
: "a" (v), "c"(n)); : "a" (v), "c"(n));
} }
void *memset(void *base, uint8_t v, size_t n) static inline void x86_memcpy(void *d, const void *s, size_t slen)
{
/*
* Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended
* to use it when possible.
*/
if ((base != NULL) && (n != 0U)) {
memset_erms(base, v, n);
}
return base;
}
void memcpy_erms(void *d, const void *s, size_t slen)
{ {
asm volatile ("rep; movsb" asm volatile ("rep; movsb"
: "=&D"(d), "=&S"(s) : "=&D"(d), "=&S"(s)
@@ -32,8 +20,7 @@ void memcpy_erms(void *d, const void *s, size_t slen)
: "memory"); : "memory");
} }
/* copy data from tail to head (backwards) with ERMS (Enhanced REP MOVSB/STOSB) */ static inline void x86_memcpy_backwards(void *d, const void *s, size_t slen)
void memcpy_erms_backwards(void *d, const void *s, size_t slen)
{ {
asm volatile ("std; rep; movsb; cld" asm volatile ("std; rep; movsb; cld"
: "=&D"(d), "=&S"(s) : "=&D"(d), "=&S"(s)
@@ -41,30 +28,29 @@ void memcpy_erms_backwards(void *d, const void *s, size_t slen)
: "memory"); : "memory");
} }
/* void *arch_memset(void *base, uint8_t v, size_t n)
* @brief Copies at most slen bytes from src address to dest address, up to dmax.
*
* INPUTS
*
* @param[in] d pointer to Destination address
* @param[in] dmax maximum length of dest
* @param[in] s pointer to Source address
* @param[in] slen maximum number of bytes of src to copy
*
* @return 0 for success and -1 for runtime-constraint violation.
*/
int32_t memcpy_s(void *d, size_t dmax, const void *s, size_t slen)
{ {
int32_t ret = -1; /*
* Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended
if ((d != NULL) && (s != NULL) && (dmax >= slen) && ((d > (s + slen)) || (s > (d + dmax)))) { * to use it when possible.
if (slen != 0U) { */
memcpy_erms(d, s, slen); if ((base != NULL) && (n != 0U)) {
} x86_memset(base, v, n);
ret = 0;
} else {
(void)memset(d, 0U, dmax);
} }
return ret; return base;
}
void arch_memcpy(void *d, const void *s, size_t slen)
{
if ((d != NULL) && (s != NULL) && (slen != 0U)) {
x86_memcpy(d, s, slen);
}
}
void arch_memcpy_backwards(void *d, const void *s, size_t slen)
{
if ((d != NULL) && (s != NULL) && (slen != 0U)) {
x86_memcpy_backwards(d, s, slen);
}
} }

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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2022 Intel Corporation. * Copyright (C) 2018-2025 Intel Corporation.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@@ -184,8 +184,8 @@ void schedule(void)
/* If we picked different sched object, switch context */ /* If we picked different sched object, switch context */
if (prev != next) { if (prev != next) {
if (prev != NULL) { if (prev != NULL) {
memcpy_erms(name, prev->name, 4); memcpy(name, prev->name, 4);
memcpy_erms(name + 4, next->name, 4); memcpy(name + 4, next->name, 4);
memset(name + 8, 0, sizeof(name) - 8); memset(name + 8, 0, sizeof(name) - 8);
TRACE_16STR(TRACE_SCHED_NEXT, name); TRACE_16STR(TRACE_SCHED_NEXT, name);
if (prev->switch_out != NULL) { if (prev->switch_out != NULL) {

View File

@@ -315,7 +315,7 @@ static void handle_delete_key(void)
set_cursor_pos(delta); set_cursor_pos(delta);
memcpy_erms(p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset, memcpy(p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset,
p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset + 1, delta); p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset + 1, delta);
/* Null terminate the last character to erase it */ /* Null terminate the last character to erase it */
@@ -450,7 +450,7 @@ static void handle_backspace_key(void)
shell_puts(" \b"); shell_puts(" \b");
set_cursor_pos(delta); set_cursor_pos(delta);
memcpy_erms(p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset - 1, memcpy(p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset - 1,
p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset, delta); p_shell->buffered_line[p_shell->input_line_active] + p_shell->cursor_offset, delta);
} }
@@ -469,7 +469,7 @@ static void handle_input_char(char ch)
/* move the input from cursor offset back first */ /* move the input from cursor offset back first */
if (delta > 0) { if (delta > 0) {
memcpy_erms_backwards(p_shell->buffered_line[p_shell->input_line_active] + p_shell->input_line_len, memcpy_backwards(p_shell->buffered_line[p_shell->input_line_active] + p_shell->input_line_len,
p_shell->buffered_line[p_shell->input_line_active] + p_shell->input_line_len - 1, delta); p_shell->buffered_line[p_shell->input_line_active] + p_shell->input_line_len - 1, delta);
} }

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@@ -0,0 +1,10 @@
/*
* Copyright (C) 2018-2025 Intel Corporation.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef X86_LIB_MEMORY_H
#define X86_LIB_MEMORY_H
#define HAS_ARCH_MEMORY_LIB
#endif /* X86_LIB_MEMORY_H */

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@@ -0,0 +1,37 @@
/*
* Copyright (C) 2025 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MEMORY_LIB_H
#define MEMORY_LIB_H
#include <types.h>
#include <asm/lib/memory.h>
#ifdef HAS_ARCH_MEMORY_LIB
void *arch_memset(void *base, uint8_t v, size_t n);
void arch_memcpy(void *d, const void *s, size_t slen);
void arch_memcpy_backwards(void *d, const void *s, size_t slen);
static inline void *memset(void *base, uint8_t v, size_t n) {
return arch_memset(base, v, n);
}
static inline void memcpy(void *d, const void *s, size_t slen) {
return arch_memcpy(d, s, slen);
}
static inline void memcpy_backwards(void *d, const void *s, size_t slen) {
return arch_memcpy_backwards(d, s, slen);
}
#else
void *memset(void *base, uint8_t v, size_t n);
void memcpy(void *d, const void *s, size_t slen);
void memcpy_backwards(void *d, const void *s, size_t slen);
#endif
int32_t memcpy_s(void *d, size_t dmax, const void *s, size_t slen);
#endif /* MEMORY_LIB_H */

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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2022 Intel Corporation. * Copyright (C) 2018-2025 Intel Corporation.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@@ -8,7 +8,7 @@
#define RTL_H #define RTL_H
#include <types.h> #include <types.h>
#include <memory.h>
union u_qword { union u_qword {
struct { struct {
uint32_t low; uint32_t low;
@@ -40,10 +40,6 @@ int32_t strncmp(const char *s1_arg, const char *s2_arg, size_t n_arg);
int32_t strncpy_s(char *d, size_t dmax, const char *s, size_t slen); int32_t strncpy_s(char *d, size_t dmax, const char *s, size_t slen);
char *strchr(char *s_arg, char ch); char *strchr(char *s_arg, char ch);
size_t strnlen_s(const char *str_arg, size_t maxlen_arg); size_t strnlen_s(const char *str_arg, size_t maxlen_arg);
void *memset(void *base, uint8_t v, size_t n);
int32_t memcpy_s(void *d, size_t dmax, const void *s, size_t slen);
void memcpy_erms(void *d, const void *s, size_t slen);
void memcpy_erms_backwards(void *d, const void *s, size_t slen);
int64_t strtol_deci(const char *nptr); int64_t strtol_deci(const char *nptr);
uint64_t strtoul_hex(const char *nptr); uint64_t strtoul_hex(const char *nptr);
char *strstr_s(const char *str1, size_t maxlen1, const char *str2, size_t maxlen2); char *strstr_s(const char *str1, size_t maxlen1, const char *str2, size_t maxlen2);

68
hypervisor/lib/memory.c Normal file
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@@ -0,0 +1,68 @@
/*
* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Authors:
* Haicheng Li <haicheng.li@intel.com>
*/
#include <types.h>
#include <memory.h>
#ifndef HAS_ARCH_MEMORY_LIB
void *memset(void *base, uint8_t v, size_t n)
{
uint8_t *p = (uint8_t *)base;
for (size_t i = 0U; i < n; i++) {
*p++ = v;
}
return base;
}
void *memset_s(void *base, uint8_t v, size_t n)
{
if ((base != NULL) && (n != 0U)) {
(void)memset(base, v, n);
}
return base;
}
void memcpy(void *d, const void *s, size_t slen)
{
uint8_t *dst = (uint8_t *)d;
const uint8_t *src = (const uint8_t *)s;
for (size_t i = 0U; i < slen; i++) {
*dst++ = *src++;
}
}
void memcpy_backwards(void *d, const void *s, size_t slen)
{
uint8_t *dst = (uint8_t *)d + slen - 1;
const uint8_t *src = (const uint8_t *)s + slen - 1;
for (size_t i = 0U; i < slen; i++) {
*dst-- = *src--;
}
}
#endif
int32_t memcpy_s(void *d, size_t dmax, const void *s, size_t slen)
{
int32_t ret = -1;
if ((d != NULL) && (s != NULL) && (dmax >= slen) && ((d > (s + slen)) || (s > (d + dmax)))) {
if (slen != 0U) {
memcpy(d, s, slen);
}
ret = 0;
} else {
(void)memset(d, 0U, dmax);
}
return ret;
}