diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index ba5caea2b..809c52ebe 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -77,6 +77,8 @@ static uint32_t emulated_guest_msrs[NUM_EMULATED_MSRS] = {
 
 	MSR_TEST_CTL,
 
+	MSR_PLATFORM_INFO,
+
 	/* VMX: CPUID.01H.ECX[5] */
 #ifdef CONFIG_NVMX_ENABLED
 	LIST_OF_VMX_MSRS,
@@ -770,6 +772,19 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
 		}
 		break;
 	}
+	case MSR_PLATFORM_INFO:
+	{
+		if (is_service_vm(vcpu->vm)) {
+			v = msr_read(msr);
+			v &= MSR_PLATFORM_INFO_MAX_NON_TURBO_LIM_RATIO_MASK |
+			     MSR_PLATFORM_INFO_MAX_EFFICIENCY_RATIO_MASK |
+			     MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK |
+			     MSR_PLATFORM_INFO_SAMPLE_PART;
+		} else {
+			err = -EACCES;
+		}
+		break;
+	}
 #ifdef CONFIG_VCAT_ENABLED
 	case MSR_IA32_L2_MASK_BASE ... (MSR_IA32_L2_MASK_BASE +  NUM_CAT_L2_MSRS - 1U):
 	case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE +  NUM_CAT_L3_MSRS - 1U):
diff --git a/hypervisor/include/arch/x86/asm/guest/vcpu.h b/hypervisor/include/arch/x86/asm/guest/vcpu.h
index 925dab65d..825f4a672 100644
--- a/hypervisor/include/arch/x86/asm/guest/vcpu.h
+++ b/hypervisor/include/arch/x86/asm/guest/vcpu.h
@@ -175,7 +175,7 @@ enum reset_mode;
 #define SECURE_WORLD	1
 
 #define NUM_WORLD_MSRS		2U
-#define NUM_COMMON_MSRS		24U
+#define NUM_COMMON_MSRS		25U
 
 #ifdef CONFIG_VCAT_ENABLED
 #define NUM_CAT_L2_MSRS	MAX_CACHE_CLOS_NUM_ENTRIES
diff --git a/hypervisor/include/arch/x86/asm/msr.h b/hypervisor/include/arch/x86/asm/msr.h
index 44ed375ff..dbb43254c 100644
--- a/hypervisor/include/arch/x86/asm/msr.h
+++ b/hypervisor/include/arch/x86/asm/msr.h
@@ -673,4 +673,10 @@ void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu);
 /* Flush L1 D-cache */
 #define IA32_L1D_FLUSH				(1UL << 0U)
 
+/* PLATFORM INFO bits */
+#define MSR_PLATFORM_INFO_MAX_NON_TURBO_LIM_RATIO_MASK	(0x000000000000ff00UL)	/* 15:8 */
+#define MSR_PLATFORM_INFO_MAX_EFFICIENCY_RATIO_MASK	(0x0000ff0000000000UL)	/* 47:40 */
+#define MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK	(0x00ff000000000000UL)	/* 55:48 */
+#define MSR_PLATFORM_INFO_SAMPLE_PART			(1UL << 27U)
+
 #endif /* MSR_H */