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hv:rename several variables and api for ioapic

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rename:
  ioapic_get_gsi_irq_addr --> gsi_to_ioapic_base
  ioapic_addr -->ioapic_base

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
This commit is contained in:
Mingqiang Chi 2020-03-10 14:30:27 +08:00 committed by Eddie Dong
parent fa74bf401d
commit 790614e952
3 changed files with 18 additions and 18 deletions
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30
hypervisor/arch/x86/ioapic.c
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@ -99,12 +99,12 @@ uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index)
} }
/* /*
* @pre irq_num < NR_MAX_GSI * @pre gsi < NR_MAX_GSI
*/ */
void *ioapic_get_gsi_irq_addr(uint32_t irq_num) void *gsi_to_ioapic_base(uint32_t gsi)
{ {
return gsi_table_data[irq_num].addr; return gsi_table_data[gsi].addr;
} }
uint32_t ioapic_get_nr_gsi(void) uint32_t ioapic_get_nr_gsi(void)
@ -162,20 +162,20 @@ get_ioapic_base(uint8_t apic_id)
return ioapic_array[apic_id].addr; return ioapic_array[apic_id].addr;
} }
void ioapic_get_rte_entry(void *ioapic_addr, uint32_t pin, union ioapic_rte *rte) void ioapic_get_rte_entry(void *ioapic_base, uint32_t pin, union ioapic_rte *rte)
{ {
uint32_t rte_addr = (pin * 2U) + 0x10U; uint32_t rte_addr = (pin * 2U) + 0x10U;
rte->u.lo_32 = ioapic_read_reg32(ioapic_addr, rte_addr); rte->u.lo_32 = ioapic_read_reg32(ioapic_base, rte_addr);
rte->u.hi_32 = ioapic_read_reg32(ioapic_addr, rte_addr + 1U); rte->u.hi_32 = ioapic_read_reg32(ioapic_base, rte_addr + 1U);
} }
static inline void static inline void
ioapic_set_rte_entry(void *ioapic_addr, ioapic_set_rte_entry(void *ioapic_base,
uint32_t pin, union ioapic_rte rte) uint32_t pin, union ioapic_rte rte)
{ {
uint32_t rte_addr = (pin * 2U) + 0x10U; uint32_t rte_addr = (pin * 2U) + 0x10U;
ioapic_write_reg32(ioapic_addr, rte_addr, rte.u.lo_32); ioapic_write_reg32(ioapic_base, rte_addr, rte.u.lo_32);
ioapic_write_reg32(ioapic_addr, rte_addr + 1U, rte.u.hi_32); ioapic_write_reg32(ioapic_base, rte_addr + 1U, rte.u.hi_32);
} }
static inline union ioapic_rte static inline union ioapic_rte
@ -233,12 +233,12 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
static void ioapic_set_routing(uint32_t gsi, uint32_t vr) static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
{ {
void *addr; void *ioapic_base;
union ioapic_rte rte; union ioapic_rte rte;
addr = gsi_table_data[gsi].addr; ioapic_base = gsi_to_ioapic_base(gsi);
rte = create_rte_for_gsi_irq(gsi, vr); rte = create_rte_for_gsi_irq(gsi, vr);
ioapic_set_rte_entry(addr, gsi_table_data[gsi].pin, rte); ioapic_set_rte_entry(ioapic_base, gsi_table_data[gsi].pin, rte);
if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) { if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
set_irq_trigger_mode(gsi, true); set_irq_trigger_mode(gsi, true);
@ -259,7 +259,7 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
void *addr; void *addr;
if (ioapic_irq_is_gsi(irq)) { if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr; addr = gsi_to_ioapic_base(irq);
ioapic_get_rte_entry(addr, gsi_table_data[irq].pin, rte); ioapic_get_rte_entry(addr, gsi_table_data[irq].pin, rte);
} }
} }
@ -269,7 +269,7 @@ void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
void *addr; void *addr;
if (ioapic_irq_is_gsi(irq)) { if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr; addr = gsi_to_ioapic_base(irq);
ioapic_set_rte_entry(addr, gsi_table_data[irq].pin, rte); ioapic_set_rte_entry(addr, gsi_table_data[irq].pin, rte);
dev_dbg(DBG_LEVEL_IRQ, "GSI: irq:%d pin:%hhu rte:%lx", dev_dbg(DBG_LEVEL_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
@ -323,7 +323,7 @@ ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
union ioapic_rte rte; union ioapic_rte rte;
if (ioapic_irq_is_gsi(irq)) { if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr; addr = gsi_to_ioapic_base(irq);
pin = gsi_table_data[irq].pin; pin = gsi_table_data[irq].pin;
if (addr != NULL) { if (addr != NULL) {

2
hypervisor/debug/shell.c
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@ -1266,7 +1266,7 @@ static int32_t get_ioapic_info(char *str_arg, size_t str_max_len)
ioapic_nr_gsi = ioapic_get_nr_gsi (); ioapic_nr_gsi = ioapic_get_nr_gsi ();
for (irq = 0U; irq < ioapic_nr_gsi; irq++) { for (irq = 0U; irq < ioapic_nr_gsi; irq++) {
void *addr = ioapic_get_gsi_irq_addr(irq); void *addr = gsi_to_ioapic_base(irq);
uint32_t pin = ioapic_irq_to_pin(irq); uint32_t pin = ioapic_irq_to_pin(irq);
union ioapic_rte rte; union ioapic_rte rte;

4
hypervisor/include/arch/x86/ioapic.h
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@ -87,7 +87,7 @@ void resume_ioapic(void);
void ioapic_gsi_mask_irq(uint32_t irq); void ioapic_gsi_mask_irq(uint32_t irq);
void ioapic_gsi_unmask_irq(uint32_t irq); void ioapic_gsi_unmask_irq(uint32_t irq);
void ioapic_get_rte_entry(void *ioapic_addr, uint32_t pin, union ioapic_rte *rte); void ioapic_get_rte_entry(void *ioapic_base, uint32_t pin, union ioapic_rte *rte);
struct gsi_table { struct gsi_table {
uint8_t ioapic_id; uint8_t ioapic_id;
@ -95,7 +95,7 @@ struct gsi_table {
void *addr; void *addr;
}; };
void *ioapic_get_gsi_irq_addr(uint32_t irq_num); void *gsi_to_ioapic_base(uint32_t gsi);
uint32_t ioapic_get_nr_gsi(void); uint32_t ioapic_get_nr_gsi(void);
uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index); uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index);
bool ioapic_is_pin_valid(uint32_t pin); bool ioapic_is_pin_valid(uint32_t pin);