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hv:Rename several APIs for vpic and vioapic

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vpic:
   vpic_set_irq         --> vpic_set_irqline
   vpic_get_irq_trigger --> vpic_get_irqline_trigger_mode
vioapic:
   vioapic_set_irq_nolock --> vioapic_set_irqline_nolock
   vioapic_set_irq        --> vioapic_set_irqline_lock
   vioapic_send_intr      --> vioapic_generate_intr

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
This commit is contained in:
Mingqiang Chi
2019-01-07 11:39:15 +08:00
committed by wenlingz
parent 070a56dbc4
commit 7907fef59e
8 changed files with 37 additions and 42 deletions
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30
hypervisor/arch/x86/assign.c
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@@ -124,16 +124,12 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
/* init polarity & pin state */
if ((rte.full & IOAPIC_RTE_INTPOL) != 0UL) {
if (entry->polarity == 0U) {
vioapic_set_irq_nolock(vm,
(uint32_t)virt_sid->intx_id.pin,
GSI_SET_HIGH);
vioapic_set_irqline_nolock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
}
entry->polarity = 1U;
} else {
if (entry->polarity == 1U) {
vioapic_set_irq_nolock(vm,
(uint32_t)virt_sid->intx_id.pin,
GSI_SET_LOW);
vioapic_set_irqline_nolock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_LOW);
}
entry->polarity = 0U;
}
@@ -171,7 +167,7 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
/* just update trigger mode */
ioapic_get_rte(phys_irq, &phys_rte);
rte.full = phys_rte.full & (~IOAPIC_RTE_TRGRMOD);
vpic_get_irq_trigger(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
vpic_get_irqline_trigger_mode(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
if (trigger == LEVEL_TRIGGER) {
rte.full |= IOAPIC_RTE_TRGRLVL;
}
@@ -377,15 +373,15 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
if (trigger_lvl) {
if (entry->polarity != 0U) {
vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_LOW);
vioapic_set_irqline_lock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_LOW);
} else {
vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
vioapic_set_irqline_lock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
}
} else {
if (entry->polarity != 0U) {
vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_FALLING_PULSE);
vioapic_set_irqline_lock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_FALLING_PULSE);
} else {
vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
vioapic_set_irqline_lock(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
}
}
@@ -401,11 +397,11 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
enum vpic_trigger trigger;
/* VPIN_PIC src means we have vpic enabled */
vpic_get_irq_trigger(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
vpic_get_irqline_trigger_mode(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
if (trigger == LEVEL_TRIGGER) {
vpic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
vpic_set_irqline(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
} else {
vpic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
vpic_set_irqline(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
}
break;
}
@@ -476,13 +472,13 @@ void ptirq_intx_ack(struct acrn_vm *vm, uint8_t virt_pin,
switch (vpin_src) {
case PTDEV_VPIN_IOAPIC:
if (entry->polarity != 0U) {
vioapic_set_irq(vm, virt_pin, GSI_SET_HIGH);
vioapic_set_irqline_lock(vm, virt_pin, GSI_SET_HIGH);
} else {
vioapic_set_irq(vm, virt_pin, GSI_SET_LOW);
vioapic_set_irqline_lock(vm, virt_pin, GSI_SET_LOW);
}
break;
case PTDEV_VPIN_PIC:
vpic_set_irq(vm, virt_pin, GSI_SET_LOW);
vpic_set_irqline(vm, virt_pin, GSI_SET_LOW);
break;
default:
/*