mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-01-13 11:33:58 +00:00
initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Eddie Dong
lijinxia
389
hypervisor/arch/x86/guest/guest.c
Normal file
389
hypervisor/arch/x86/guest/guest.c
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@@ -0,0 +1,389 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <bsp_cfg.h>
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#include <bsp_extern.h>
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#include <acrn_hv_defs.h>
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#include <hv_debug.h>
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#include <multiboot.h>
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#define BOOT_ARGS_LOAD_ADDR 0x24EFC000
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#define ACRN_DBG_GUEST 6
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/* for VM0 e820 */
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uint32_t e820_entries;
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struct e820_entry e820[E820_MAX_ENTRIES];
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struct e820_mem_params e820_mem;
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inline bool
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is_vm0(struct vm *vm)
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{
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return (vm->attr.boot_idx & 0x7F) == 0;
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}
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inline struct vcpu *vcpu_from_vid(struct vm *vm, int vcpu_id)
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{
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int i;
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struct vcpu *vcpu;
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foreach_vcpu(i, vm, vcpu) {
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if (vcpu->vcpu_id == vcpu_id)
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return vcpu;
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}
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return NULL;
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}
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inline struct vcpu *vcpu_from_pid(struct vm *vm, int pcpu_id)
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{
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int i;
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struct vcpu *vcpu;
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foreach_vcpu(i, vm, vcpu) {
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if (vcpu->pcpu_id == pcpu_id)
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return vcpu;
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}
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return NULL;
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}
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inline struct vcpu *get_primary_vcpu(struct vm *vm)
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{
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int i;
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struct vcpu *vcpu;
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foreach_vcpu(i, vm, vcpu) {
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if (is_vcpu_bsp(vcpu))
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return vcpu;
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}
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return NULL;
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}
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inline uint64_t vcpumask2pcpumask(struct vm *vm, uint64_t vdmask)
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{
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int vcpu_id;
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uint64_t dmask = 0;
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struct vcpu *vcpu;
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while ((vcpu_id = bitmap_ffs(&vdmask)) >= 0) {
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bitmap_clr(vcpu_id, &vdmask);
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vcpu = vcpu_from_vid(vm, vcpu_id);
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ASSERT(vcpu, "vcpu_from_vid failed");
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bitmap_set(vcpu->pcpu_id, &dmask);
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}
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return dmask;
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}
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inline bool vm_lapic_disabled(struct vm *vm)
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{
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int i;
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struct vcpu *vcpu;
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foreach_vcpu(i, vm, vcpu) {
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if (vlapic_enabled(vcpu->arch_vcpu.vlapic))
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return false;
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}
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return true;
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}
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int init_vm0_boot_info(struct vm *vm)
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{
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struct multiboot_module *mods = NULL;
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struct multiboot_info *mbi = NULL;
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if (!is_vm0(vm)) {
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pr_err("just for vm0 to get info!");
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return -EINVAL;
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}
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if (boot_regs[0] != MULTIBOOT_INFO_MAGIC) {
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ASSERT(0, "no multiboot info found");
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return -EINVAL;
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}
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mbi = (struct multiboot_info *)((uint64_t)boot_regs[1]);
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dev_dbg(ACRN_DBG_GUEST, "Multiboot detected, flag=0x%x", mbi->mi_flags);
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if (!(mbi->mi_flags & MULTIBOOT_INFO_HAS_MODS)) {
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ASSERT(0, "no sos kernel info found");
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return -EINVAL;
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}
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dev_dbg(ACRN_DBG_GUEST, "mod counts=%d\n", mbi->mi_mods_count);
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/* mod[0] is for kernel&cmdline, other mod for ramdisk/firmware info*/
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mods = (struct multiboot_module *)(uint64_t)mbi->mi_mods_addr;
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dev_dbg(ACRN_DBG_GUEST, "mod0 start=0x%x, end=0x%x",
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mods[0].mm_mod_start, mods[0].mm_mod_end);
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dev_dbg(ACRN_DBG_GUEST, "cmd addr=0x%x, str=%s", mods[0].mm_string,
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(char *) (uint64_t)mods[0].mm_string);
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vm->sw.kernel_type = VM_LINUX_GUEST;
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vm->sw.kernel_info.kernel_src_addr =
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(void *)(uint64_t)mods[0].mm_mod_start;
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vm->sw.kernel_info.kernel_size =
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mods[0].mm_mod_end - mods[0].mm_mod_start;
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vm->sw.kernel_info.kernel_load_addr =
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(void *)(uint64_t)mods[0].mm_mod_start;
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vm->sw.linux_info.bootargs_src_addr =
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(void *)(uint64_t)mods[0].mm_string;
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vm->sw.linux_info.bootargs_load_addr =
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(void *)BOOT_ARGS_LOAD_ADDR;
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vm->sw.linux_info.bootargs_size =
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strnlen_s((char *)(uint64_t) mods[0].mm_string, MEM_2K);
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return 0;
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}
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uint64_t gva2gpa(struct vm *vm, uint64_t cr3, uint64_t gva)
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{
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int level, index, shift;
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uint64_t *base, addr, entry, page_size;
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uint64_t gpa = 0;
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addr = cr3;
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for (level = 3; level >= 0; level--) {
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addr = addr & IA32E_REF_MASK;
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base = GPA2HVA(vm, addr);
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ASSERT(base != NULL, "invalid ptp base.");
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shift = level * 9 + 12;
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index = (gva >> shift) & 0x1FF;
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page_size = 1UL << shift;
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entry = base[index];
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if (level > 0 && (entry & MMU_32BIT_PDE_PS) != 0)
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break;
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addr = entry;
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}
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entry >>= shift; entry <<= (shift + 12); entry >>= 12;
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gpa = entry | (gva & (page_size - 1));
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return gpa;
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}
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void init_e820(void)
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{
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unsigned int i;
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if (boot_regs[0] == MULTIBOOT_INFO_MAGIC) {
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struct multiboot_info *mbi =
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(struct multiboot_info *)((uint64_t)boot_regs[1]);
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pr_info("Multiboot info detected\n");
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if (mbi->mi_flags & 0x40) {
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struct multiboot_mmap *mmap =
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(struct multiboot_mmap *)
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((uint64_t)mbi->mi_mmap_addr);
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e820_entries = mbi->mi_mmap_length/
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sizeof(struct multiboot_mmap);
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if (e820_entries > E820_MAX_ENTRIES) {
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pr_err("Too many E820 entries %d\n",
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e820_entries);
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e820_entries = E820_MAX_ENTRIES;
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}
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dev_dbg(ACRN_DBG_GUEST,
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"mmap length 0x%x addr 0x%x entries %d\n",
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mbi->mi_mmap_length, mbi->mi_mmap_addr,
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e820_entries);
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for (i = 0; i < e820_entries; i++) {
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e820[i].baseaddr = mmap[i].baseaddr;
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e820[i].length = mmap[i].length;
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e820[i].type = mmap[i].type;
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dev_dbg(ACRN_DBG_GUEST,
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"mmap table: %d type: 0x%x\n",
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i, mmap[i].type);
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dev_dbg(ACRN_DBG_GUEST,
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"Base: 0x%016llx length: 0x%016llx",
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mmap[i].baseaddr, mmap[i].length);
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}
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}
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} else
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ASSERT(0, "no multiboot info found");
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}
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void obtain_e820_mem_info(void)
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{
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unsigned int i;
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struct e820_entry *entry;
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e820_mem.mem_bottom = UINT64_MAX;
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e820_mem.mem_top = 0x00;
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e820_mem.max_ram_blk_base = 0;
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e820_mem.max_ram_blk_size = 0;
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for (i = 0; i < e820_entries; i++) {
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entry = &e820[i];
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if (e820_mem.mem_bottom > entry->baseaddr)
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e820_mem.mem_bottom = entry->baseaddr;
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if (entry->baseaddr + entry->length
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> e820_mem.mem_top) {
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e820_mem.mem_top = entry->baseaddr
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+ entry->length;
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}
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if (entry->baseaddr == UOS_DEFAULT_START_ADDR
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&& entry->type == E820_TYPE_RAM) {
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e820_mem.max_ram_blk_base =
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entry->baseaddr;
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e820_mem.max_ram_blk_size = entry->length;
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}
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}
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}
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static void rebuild_vm0_e820(void)
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{
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unsigned int i;
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uint64_t entry_start;
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uint64_t entry_end;
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uint64_t hv_start = CONFIG_RAM_START;
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uint64_t hv_end = hv_start + CONFIG_RAM_SIZE;
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struct e820_entry *entry, new_entry = {0};
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/* hypervisor mem need be filter out from e820 table
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* it's hv itself + other hv reserved mem like vgt etc
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*/
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for (i = 0; i < e820_entries; i++) {
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entry = &e820[i];
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entry_start = entry->baseaddr;
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entry_end = entry->baseaddr + entry->length;
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/* No need handle in these cases*/
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if (entry->type != E820_TYPE_RAM || entry_end <= hv_start
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|| entry_start >= hv_end) {
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continue;
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}
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/* filter out hv mem and adjust length of this entry*/
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if (entry_start < hv_start && entry_end <= hv_end) {
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entry->length = hv_start - entry_start;
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continue;
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}
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/* filter out hv mem and need to create a new entry*/
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if (entry_start < hv_start && entry_end > hv_end) {
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entry->length = hv_start - entry_start;
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new_entry.baseaddr = hv_end;
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new_entry.length = entry_end - hv_end;
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new_entry.type = E820_TYPE_RAM;
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continue;
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}
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/* This entry is within the range of hv mem
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* change to E820_TYPE_RESERVED
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*/
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if (entry_start >= hv_start && entry_end <= hv_end) {
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entry->type = E820_TYPE_RESERVED;
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continue;
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}
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if (entry_start >= hv_start && entry_start < hv_end
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&& entry_end > hv_end) {
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entry->baseaddr = hv_end;
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entry->length = entry_end - hv_end;
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continue;
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}
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}
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if (new_entry.length > 0) {
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e820_entries++;
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ASSERT(e820_entries <= E820_MAX_ENTRIES,
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"e820 entry overflow");
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entry = &e820[e820_entries - 1];
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entry->baseaddr = new_entry.baseaddr;
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entry->length = new_entry.length;
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entry->type = new_entry.type;
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}
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}
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int prepare_vm0_memmap_and_e820(struct vm *vm)
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{
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unsigned int i;
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uint32_t attr_wb = (MMU_MEM_ATTR_READ |
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MMU_MEM_ATTR_WRITE |
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MMU_MEM_ATTR_EXECUTE |
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MMU_MEM_ATTR_WB_CACHE);
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uint32_t attr_uc = (MMU_MEM_ATTR_READ |
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MMU_MEM_ATTR_WRITE |
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MMU_MEM_ATTR_EXECUTE |
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MMU_MEM_ATTR_UNCACHED);
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struct e820_entry *entry;
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ASSERT(is_vm0(vm), "This func only for vm0");
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rebuild_vm0_e820();
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dev_dbg(ACRN_DBG_GUEST,
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"vm0: bottom memory - 0x%llx, top memory - 0x%llx\n",
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e820_mem.mem_bottom, e820_mem.mem_top);
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/* create real ept map for all ranges with UC */
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ept_mmap(vm, e820_mem.mem_bottom, e820_mem.mem_bottom,
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(e820_mem.mem_top - e820_mem.mem_bottom),
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MAP_MMIO, attr_uc);
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/* update ram entries to WB attr */
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for (i = 0; i < e820_entries; i++) {
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entry = &e820[i];
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if (entry->type == E820_TYPE_RAM)
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ept_mmap(vm, entry->baseaddr, entry->baseaddr,
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entry->length, MAP_MEM, attr_wb);
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}
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dev_dbg(ACRN_DBG_GUEST, "VM0 e820 layout:\n");
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for (i = 0; i < e820_entries; i++) {
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entry = &e820[i];
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dev_dbg(ACRN_DBG_GUEST,
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"e820 table: %d type: 0x%x", i, entry->type);
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dev_dbg(ACRN_DBG_GUEST,
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"BaseAddress: 0x%016llx length: 0x%016llx\n",
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entry->baseaddr, entry->length);
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}
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/* unmap hypervisor itself for safety
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* will cause EPT violation if sos accesses hv memory
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*/
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ept_mmap(vm, CONFIG_RAM_START, CONFIG_RAM_START,
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CONFIG_RAM_SIZE, MAP_UNMAP, 0);
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return 0;
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}
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