initial import

internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/bsp/sbl/vm_description.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2018 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <hypervisor.h>
+#include <hv_lib.h>
+#include <acrn_common.h>
+#include <hv_arch.h>
+
+#define NUM_USER_VMS    2
+
+/* Number of CPUs in VM0 */
+#define VM0_NUM_CPUS    1
+
+/* Logical CPU IDs assigned to VM0 */
+int VM0_CPUS[VM0_NUM_CPUS] = {0};
+
+/* Number of CPUs in VM1 */
+#define VM1_NUM_CPUS    2
+
+/* Logical CPU IDs assigned with VM1 */
+int VM1_CPUS[VM1_NUM_CPUS] = {3, 1};
+
+const struct vm_description_array vm_desc = {
+	/* Number of user virtual machines */
+	.num_vm_desc = NUM_USER_VMS,
+
+	/* Virtual Machine descriptions */
+	.vm_desc_array = {
+		{
+		/* Internal variable, MUSTBE init to -1 */
+		.vm_attr_name = "vm_0",
+		.vm_hw_num_cores = VM0_NUM_CPUS,
+		.vm_hw_logical_core_ids = &VM0_CPUS[0],
+		.vm_state_info_privilege = VM_PRIVILEGE_LEVEL_HIGH,
+		.vm_created = false,
+		},
+	}
+};
+
+const struct vm_description_array *get_vm_desc_base(void)
+{
+	return &vm_desc;
+}