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https://github.com/projectacrn/acrn-hypervisor.git
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initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Eddie Dong
lijinxia
622
hypervisor/include/arch/x86/io.h
Normal file
622
hypervisor/include/arch/x86/io.h
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@@ -0,0 +1,622 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef IO_H
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#define IO_H
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/* Definition of a IO port range */
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struct vm_io_range {
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uint16_t base; /* IO port base */
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uint16_t len; /* IO port range */
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int flags; /* IO port attributes */
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};
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/* Write 1 byte to specified I/O port */
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static inline void io_write_byte(uint8_t value, uint16_t port)
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{
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asm volatile ("outb %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 1 byte from specified I/O port */
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static inline uint8_t io_read_byte(uint16_t port)
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{
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uint8_t value;
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asm volatile ("inb %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 2 bytes to specified I/O port */
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static inline void io_write_word(uint16_t value, uint16_t port)
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{
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asm volatile ("outw %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 2 bytes from specified I/O port */
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static inline uint16_t io_read_word(uint16_t port)
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{
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uint16_t value;
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asm volatile ("inw %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 4 bytes to specified I/O port */
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static inline void io_write_long(uint32_t value, uint16_t port)
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{
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asm volatile ("outl %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 4 bytes from specified I/O port */
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static inline uint32_t io_read_long(uint16_t port)
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{
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uint32_t value;
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asm volatile ("inl %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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static inline void io_write(uint32_t v, ioport_t addr, size_t sz)
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{
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if (sz == 1)
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io_write_byte(v, addr);
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else if (sz == 2)
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io_write_word(v, addr);
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else
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io_write_long(v, addr);
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}
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static inline uint32_t io_read(ioport_t addr, size_t sz)
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{
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if (sz == 1)
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return io_read_byte(addr);
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if (sz == 2)
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return io_read_word(addr);
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return io_read_long(addr);
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}
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struct vm_io_handler;
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struct vm;
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struct vcpu;
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typedef
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uint32_t (*io_read_fn_t)(struct vm_io_handler *, struct vm *,
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ioport_t, size_t);
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typedef
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void (*io_write_fn_t)(struct vm_io_handler *, struct vm *,
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ioport_t, size_t, uint32_t);
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/* Describes a single IO handler description entry. */
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struct vm_io_handler_desc {
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/** The base address of the IO range for this description. */
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ioport_t addr;
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/** The number of bytes covered by this description. */
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size_t len;
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/** A pointer to the "read" function.
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*
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* The read function is called from the hypervisor whenever
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* a read access to a range described in "ranges" occur.
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* The arguments to the callback are:
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*
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* - The address of the port to read from.
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* - The width of the read operation (1,2 or 4).
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*
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* The implementation must return the ports content as
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* byte, word or doubleword (depending on the width).
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*
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* If the pointer is null, a read of 1's is assumed.
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*/
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io_read_fn_t io_read;
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/** A pointer to the "write" function.
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*
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* The write function is called from the hypervisor code
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* whenever a write access to a range described in "ranges"
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* occur. The arguments to the callback are:
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*
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* - The address of the port to write to.
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* - The width of the write operation (1,2 or 4).
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* - The value to write as byte, word or doubleword
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* (depending on the width)
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*
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* The implementation must write the value to the port.
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*
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* If the pointer is null, the write access is ignored.
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*/
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io_write_fn_t io_write;
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};
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struct vm_io_handler {
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struct vm_io_handler *next;
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struct vm_io_handler_desc desc;
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};
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#define IO_ATTR_R 0
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#define IO_ATTR_RW 1
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#define IO_ATTR_NO_ACCESS 2
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/* External Interfaces */
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int io_instr_handler(struct vcpu *vcpu);
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void setup_io_bitmap(struct vm *vm);
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void free_io_emulation_resource(struct vm *vm);
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void register_io_emulation_handler(struct vm *vm, struct vm_io_range *range,
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io_read_fn_t io_read_fn_ptr,
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io_write_fn_t io_write_fn_ptr);
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int dm_emulate_pio_post(struct vcpu *vcpu);
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/** Writes a 32 bit value to a memory mapped IO device.
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*
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* @param value The 32 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_long(uint32_t value, mmio_addr_t addr)
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{
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*((uint32_t *)addr) = value;
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}
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/** Writes a 16 bit value to a memory mapped IO device.
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*
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* @param value The 16 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_word(uint32_t value, mmio_addr_t addr)
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{
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*((uint16_t *)addr) = value;
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}
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/** Writes an 8 bit value to a memory mapped IO device.
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*
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* @param value The 8 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_byte(uint32_t value, mmio_addr_t addr)
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{
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*((uint8_t *)addr) = value;
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}
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/** Reads a 32 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 32 bit value read from the given address.
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*/
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static inline uint32_t mmio_read_long(mmio_addr_t addr)
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{
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return *((uint32_t *)addr);
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}
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/** Reads a 16 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 16 bit value read from the given address.
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*/
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static inline uint16_t mmio_read_word(mmio_addr_t addr)
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{
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return *((uint16_t *)addr);
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}
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/** Reads an 8 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 8 bit value read from the given address.
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*/
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static inline uint8_t mmio_read_byte(mmio_addr_t addr)
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{
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return *((uint8_t *)addr);
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}
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/** Sets bits in a 32 bit value from a memory mapped IO device.
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*
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* @param mask Contains the bits to set at the memory address.
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* Bits set in this mask are set in the memory
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* location.
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* @param addr The memory address to read from/write to.
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*/
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static inline void mmio_or_long(uint32_t mask, mmio_addr_t addr)
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{
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*((uint32_t *)addr) |= mask;
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}
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/** Sets bits in a 16 bit value from a memory mapped IO device.
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*
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* @param mask Contains the bits to set at the memory address.
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* Bits set in this mask are set in the memory
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* location.
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* @param addr The memory address to read from/write to.
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*/
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static inline void mmio_or_word(uint32_t mask, mmio_addr_t addr)
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{
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*((uint16_t *)addr) |= mask;
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}
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/** Sets bits in an 8 bit value from a memory mapped IO device.
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*
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* @param mask Contains the bits to set at the memory address.
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* Bits set in this mask are set in the memory
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* location.
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* @param addr The memory address to read from/write to.
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*/
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static inline void mmio_or_byte(uint32_t mask, mmio_addr_t addr)
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{
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*((uint8_t *)addr) |= mask;
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}
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|
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/** Clears bits in a 32 bit value from a memory mapped IO device.
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*
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* @param mask Contains the bits to clear at the memory address.
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* Bits set in this mask are cleared in the memory
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* location.
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* @param addr The memory address to read from/write to.
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*/
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static inline void mmio_and_long(uint32_t mask, mmio_addr_t addr)
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{
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*((uint32_t *)addr) &= ~mask;
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}
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/** Clears bits in a 16 bit value from a memory mapped IO device.
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*
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* @param mask Contains the bits to clear at the memory address.
|
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* Bits set in this mask are cleared in the memory
|
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* location.
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* @param addr The memory address to read from/write to.
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*/
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static inline void mmio_and_word(uint32_t mask, mmio_addr_t addr)
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{
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*((uint16_t *)addr) &= ~mask;
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}
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|
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/** Clears bits in an 8 bit value from a memory mapped IO device.
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*
|
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* @param mask Contains the bits to clear at the memory address.
|
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* Bits set in this mask are cleared in the memory
|
||||
* location.
|
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* @param addr The memory address to read from/write to.
|
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*/
|
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static inline void mmio_and_byte(uint32_t mask, mmio_addr_t addr)
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{
|
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*((uint8_t *)addr) &= ~mask;
|
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}
|
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|
||||
/** Performs a read-modify-write cycle for a 32 bit value from a MMIO device.
|
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*
|
||||
* Reads a 32 bit value from a memory mapped IO device, sets and clears
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* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
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* @param addr The memory address to read from/write to.
|
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*/
|
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static inline void mmio_rmw_long(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
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*((uint32_t *)addr) =
|
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(*((uint32_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Performs a read-modify-write cycle for a 16 bit value from a MMIO device.
|
||||
*
|
||||
* Reads a 16 bit value from a memory mapped IO device, sets and clears
|
||||
* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void mmio_rmw_word(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
||||
*((uint16_t *)addr) =
|
||||
(*((uint16_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Performs a read-modify-write cycle for an 8 bit value from a MMIO device.
|
||||
*
|
||||
* Reads an 8 bit value from a memory mapped IO device, sets and clears
|
||||
* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void mmio_rmw_byte(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
||||
*((uint8_t *)addr) = (*((uint8_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Writes a 32 bit value to a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param value The 32 bit value to write.
|
||||
* @param addr The memory address to write to.
|
||||
*/
|
||||
static inline void __mmio_write_long(uint32_t value, mmio_addr_t addr)
|
||||
{
|
||||
*((uint32_t *)addr) = value;
|
||||
}
|
||||
|
||||
/** Writes a 16 bit value to a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param value The 16 bit value to write.
|
||||
* @param addr The memory address to write to.
|
||||
*/
|
||||
static inline void __mmio_write_word(uint32_t value, mmio_addr_t addr)
|
||||
{
|
||||
*((uint16_t *)addr) = value;
|
||||
}
|
||||
|
||||
/** Writes an 8 bit value to a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param value The 8 bit value to write.
|
||||
* @param addr The memory address to write to.
|
||||
*/
|
||||
static inline void __mmio_write_byte(uint32_t value, mmio_addr_t addr)
|
||||
{
|
||||
*((uint8_t *)addr) = value;
|
||||
}
|
||||
|
||||
/** Reads a 32 bit value from a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param addr The memory address to read from.
|
||||
*
|
||||
* @return The 32 bit value read from the given address.
|
||||
*/
|
||||
static inline uint32_t __mmio_read_long(mmio_addr_t addr)
|
||||
{
|
||||
return *((uint32_t *)addr);
|
||||
}
|
||||
|
||||
/** Reads a 16 bit value from a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param addr The memory address to read from.
|
||||
*
|
||||
* @return The 16 bit value read from the given address.
|
||||
*/
|
||||
static inline uint16_t __mmio_read_word(mmio_addr_t addr)
|
||||
{
|
||||
return *((uint16_t *)addr);
|
||||
}
|
||||
|
||||
/** Reads an 8 bit value from a memory mapped IO device (ROM code version).
|
||||
*
|
||||
* @param addr The memory address to read from.
|
||||
*
|
||||
* @return The 32 16 value read from the given address.
|
||||
*/
|
||||
static inline uint8_t __mmio_read_byte(mmio_addr_t addr)
|
||||
{
|
||||
return *((uint8_t *)addr);
|
||||
}
|
||||
|
||||
/** Sets bits in a 32 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to set at the memory address.
|
||||
* Bits set in this mask are set in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_or_long(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint32_t *)addr) |= mask;
|
||||
}
|
||||
|
||||
/** Sets bits in a 16 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to set at the memory address.
|
||||
* Bits set in this mask are set in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_or_word(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint16_t *)addr) |= mask;
|
||||
}
|
||||
|
||||
/** Sets bits in an 8 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to set at the memory address.
|
||||
* Bits set in this mask are set in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_or_byte(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint8_t *)addr) |= mask;
|
||||
}
|
||||
|
||||
/** Clears bits in a 32 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to clear at the memory address.
|
||||
* Bits set in this mask are cleared in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_and_long(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint32_t *)addr) &= ~mask;
|
||||
}
|
||||
|
||||
/** Clears bits in a 16 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to clear at the memory address.
|
||||
* Bits set in this mask are cleared in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_and_word(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint16_t *)addr) &= ~mask;
|
||||
}
|
||||
|
||||
/** Clears bits in an 8 bit value from a MMIO device (ROM code version).
|
||||
*
|
||||
* @param mask Contains the bits to clear at the memory address.
|
||||
* Bits set in this mask are cleared in the memory
|
||||
* location.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void __mmio_and_byte(uint32_t mask, mmio_addr_t addr)
|
||||
{
|
||||
*((uint8_t *)addr) &= ~mask;
|
||||
}
|
||||
|
||||
/** Performs a read-modify-write cycle for a 32 bit value from a MMIO device
|
||||
* (ROM code version).
|
||||
*
|
||||
* Reads a 32 bit value from a memory mapped IO device, sets and clears
|
||||
* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void
|
||||
__mmio_rmw_long(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
||||
*((uint32_t *)addr) =
|
||||
(*((uint32_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Performs a read-modify-write cycle for a 16 bit value from a MMIO device
|
||||
* (ROM code version).
|
||||
*
|
||||
* Reads a 16 bit value from a memory mapped IO device, sets and clears
|
||||
* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void
|
||||
__mmio_rmw_word(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
||||
*((uint16_t *)addr) =
|
||||
(*((uint16_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Performs a read-modify-write cycle for an 8 bit value from a MMIO device
|
||||
* (ROM code version).
|
||||
*
|
||||
* Reads an 8 bit value from a memory mapped IO device, sets and clears
|
||||
* bits and writes the value back. If a bit is specified in both, the 'set'
|
||||
* and in the 'clear' mask, it is undefined whether the resulting bit is set
|
||||
* or cleared.
|
||||
*
|
||||
* @param set Contains the bits to set. Bits set in this mask
|
||||
* are set at the memory address.
|
||||
* @param clear Contains the bits to clear. Bits set in this
|
||||
* mask are cleared at the memory address.
|
||||
* @param addr The memory address to read from/write to.
|
||||
*/
|
||||
static inline void
|
||||
__mmio_rmw_byte(uint32_t set, uint32_t clear, mmio_addr_t addr)
|
||||
{
|
||||
*((uint8_t *)addr) = (*((uint8_t *)addr) & ~clear) | set;
|
||||
}
|
||||
|
||||
/** Reads a 32 Bit memory mapped IO register, mask it and write it back into
|
||||
* memory mapped IO register.
|
||||
*
|
||||
* @param addr The address of the memory mapped IO register.
|
||||
* @param mask The mask to apply to the value read.
|
||||
* @param value The 32 bit value to write.
|
||||
*/
|
||||
static inline void setl(mmio_addr_t addr, uint32_t mask, uint32_t value)
|
||||
{
|
||||
mmio_write_long((mmio_read_long(addr) & ~mask) | value, addr);
|
||||
}
|
||||
|
||||
/** Reads a 16 Bit memory mapped IO register, mask it and write it back into
|
||||
* memory mapped IO register.
|
||||
*
|
||||
* @param addr The address of the memory mapped IO register.
|
||||
* @param mask The mask to apply to the value read.
|
||||
* @param value The 16 bit value to write.
|
||||
*/
|
||||
static inline void setw(mmio_addr_t addr, uint32_t mask, uint32_t value)
|
||||
{
|
||||
mmio_write_word((mmio_read_word(addr) & ~mask) | value, addr);
|
||||
}
|
||||
|
||||
/** Reads a 8 Bit memory mapped IO register, mask it and write it back into
|
||||
* memory mapped IO register.
|
||||
*
|
||||
* @param addr The address of the memory mapped IO register.
|
||||
* @param mask The mask to apply to the value read.
|
||||
* @param value The 8 bit value to write.
|
||||
*/
|
||||
static inline void setb(mmio_addr_t addr, uint32_t mask, uint32_t value)
|
||||
{
|
||||
mmio_write_byte((mmio_read_byte(addr) & ~mask) | value, addr);
|
||||
}
|
||||
|
||||
/* MMIO memory access types */
|
||||
enum mem_io_type {
|
||||
HV_MEM_IO_READ = 0,
|
||||
HV_MEM_IO_WRITE,
|
||||
};
|
||||
|
||||
/* MMIO emulation related structures */
|
||||
#define MMIO_TRANS_VALID 1
|
||||
#define MMIO_TRANS_INVALID 0
|
||||
struct mem_io {
|
||||
uint64_t paddr; /* Physical address being accessed */
|
||||
enum mem_io_type read_write; /* 0 = read / 1 = write operation */
|
||||
uint8_t access_size; /* Access size being emulated */
|
||||
uint8_t sign_extend_read; /* 1 if sign extension required for read */
|
||||
uint64_t value; /* Value read or value to write */
|
||||
uint8_t mmio_status; /* Indicates if this MMIO transaction is valid */
|
||||
/* Used to store emulation context for this mmio transaction */
|
||||
void *private_data;
|
||||
};
|
||||
|
||||
#endif /* _IO_H defined */
|
||||
Reference in New Issue
Block a user