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hv: minor cleanup for dm/vpci code

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- It makes more sense to return bool from pci_bar_access()
- other minor changes for cleanup

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen 2018-10-24 15:54:41 -07:00 committed by lijinxia
parent bc4f82d1d1
commit 7b4b78c323
2 changed files with 12 additions and 12 deletions
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16
hypervisor/dm/hw/pci.c
View File

@ -31,8 +31,8 @@
#include <pci.h> #include <pci.h>
static spinlock_t pci_device_lock = { static spinlock_t pci_device_lock = {
.head = 0, .head = 0U,
.tail = 0 .tail = 0U
}; };
static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset) static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
@ -54,15 +54,15 @@ uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t byte
addr = pci_pdev_calc_address(pdev->bdf, offset); addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */ /* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U); pio_write32(addr, PCI_CONFIG_ADDR);
/* Read result from DATA register */ /* Read result from DATA register */
switch (bytes) { switch (bytes) {
case 1U: case 1U:
val = pio_read8(PCI_CONFIG_DATA + (offset & 3U)); val = (uint32_t)pio_read8(PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break; break;
case 2U: case 2U:
val = pio_read16(PCI_CONFIG_DATA + (offset & 2U)); val = (uint32_t)pio_read16(PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break; break;
default: default:
val = pio_read32(PCI_CONFIG_DATA); val = pio_read32(PCI_CONFIG_DATA);
@ -83,15 +83,15 @@ void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes,
addr = pci_pdev_calc_address(pdev->bdf, offset); addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */ /* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U); pio_write32(addr, PCI_CONFIG_ADDR);
/* Write value to DATA register */ /* Write value to DATA register */
switch (bytes) { switch (bytes) {
case 1U: case 1U:
pio_write8(val, PCI_CONFIG_DATA + (offset & 3U)); pio_write8((uint8_t)val, PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
break; break;
case 2U: case 2U:
pio_write16(val, PCI_CONFIG_DATA + (offset & 2U)); pio_write16((uint16_t)val, PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
break; break;
default: default:
pio_write32(val, PCI_CONFIG_DATA); pio_write32(val, PCI_CONFIG_DATA);

8
hypervisor/include/dm/pci.h
View File

@ -144,16 +144,16 @@ enum pci_bar_type {
static inline uint32_t pci_bar_offset(uint32_t idx) static inline uint32_t pci_bar_offset(uint32_t idx)
{ {
return 0x10U + (idx << 2U); return PCIR_BARS + (idx << 2U);
} }
static inline int pci_bar_access(uint32_t offset) static inline bool pci_bar_access(uint32_t offset)
{ {
if ((offset >= pci_bar_offset(0U)) if ((offset >= pci_bar_offset(0U))
&& (offset < pci_bar_offset(PCI_BAR_COUNT))) { && (offset < pci_bar_offset(PCI_BAR_COUNT))) {
return 1; return true;
} else { } else {
return 0; return false;
} }
} }