diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c index c21318e12..d1cb1b523 100644 --- a/hypervisor/arch/x86/cpu.c +++ b/hypervisor/arch/x86/cpu.c @@ -34,12 +34,12 @@ uint64_t trampoline_start16_paddr; /* TODO: add more capability per requirement */ /*APICv features*/ -#define VAPIC_FEATURE_VIRT_ACCESS (1 << 0) -#define VAPIC_FEATURE_VIRT_REG (1 << 1) -#define VAPIC_FEATURE_INTR_DELIVERY (1 << 2) -#define VAPIC_FEATURE_TPR_SHADOW (1 << 3) -#define VAPIC_FEATURE_POST_INTR (1 << 4) -#define VAPIC_FEATURE_VX2APIC_MODE (1 << 5) +#define VAPIC_FEATURE_VIRT_ACCESS (1U << 0) +#define VAPIC_FEATURE_VIRT_REG (1U << 1) +#define VAPIC_FEATURE_INTR_DELIVERY (1U << 2) +#define VAPIC_FEATURE_TPR_SHADOW (1U << 3) +#define VAPIC_FEATURE_POST_INTR (1U << 4) +#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5) struct cpu_capability { uint8_t vapic_features; @@ -59,7 +59,7 @@ int ibrs_type; inline bool cpu_has_cap(uint32_t bit) { int feat_idx = bit >> 5; - int feat_bit = bit & 0x1f; + int feat_bit = bit & 0x1fU; if (feat_idx >= FEATURE_WORDS) return false; @@ -83,7 +83,7 @@ static inline bool get_monitor_cap(void) static uint64_t get_address_mask(uint8_t limit) { - return ((1ULL << limit) - 1) & CPU_PAGE_MASK; + return ((1UL << limit) - 1UL) & CPU_PAGE_MASK; } static void get_cpu_capabilities(void) @@ -98,14 +98,14 @@ static void get_cpu_capabilities(void) cpuid(CPUID_FEATURES, &eax, &unused, &boot_cpu_data.cpuid_leaves[FEAT_1_ECX], &boot_cpu_data.cpuid_leaves[FEAT_1_EDX]); - family = (eax >> 8) & 0xff; - if (family == 0xF) - family += (eax >> 20) & 0xff; + family = (eax >> 8) & 0xffU; + if (family == 0xFU) + family += (eax >> 20) & 0xffU; boot_cpu_data.x86 = family; - model = (eax >> 4) & 0xf; - if (family >= 0x06) - model += ((eax >> 16) & 0xf) << 4; + model = (eax >> 4) & 0xfU; + if (family >= 0x06U) + model += ((eax >> 16) & 0xfU) << 4; boot_cpu_data.x86_model = model; @@ -131,8 +131,8 @@ static void get_cpu_capabilities(void) /* EAX bits 07-00: #Physical Address Bits * bits 15-08: #Linear Address Bits */ - boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xff; - boot_cpu_data.x86_phys_bits = eax & 0xff; + boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xffU; + boot_cpu_data.x86_phys_bits = eax & 0xffU; boot_cpu_data.physical_address_mask = get_address_mask(boot_cpu_data.x86_phys_bits); } @@ -629,10 +629,10 @@ static void update_trampoline_code_refs(uint64_t dest_pa) val = dest_pa + (uint64_t)trampoline_fixup_target; ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_cs); - *(uint16_t *)(ptr) = (uint16_t)(val >> 4) & 0xFFFF; + *(uint16_t *)(ptr) = (uint16_t)(val >> 4) & 0xFFFFU; ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_ip); - *(uint16_t *)(ptr) = (uint16_t)(val & 0xf); + *(uint16_t *)(ptr) = (uint16_t)(val & 0xfU); /* Update temporary page tables */ ptr = HPA2HVA(dest_pa + (uint64_t)CPU_Boot_Page_Tables_ptr); diff --git a/hypervisor/arch/x86/cpuid.c b/hypervisor/arch/x86/cpuid.c index 429b28ba6..3d37106e9 100644 --- a/hypervisor/arch/x86/cpuid.c +++ b/hypervisor/arch/x86/cpuid.c @@ -182,7 +182,7 @@ int set_vcpuid_entries(struct vm *vm) if (result != 0) return result; - times = entry.eax & 0xff; + times = entry.eax & 0xffUL; for (j = 1; j < times; j++) { init_vcpuid_entry(vm, i, j, CPUID_CHECK_SUBLEAF, &entry); diff --git a/hypervisor/include/arch/x86/cpu.h b/hypervisor/include/arch/x86/cpu.h index 359fffa35..dabb4c702 100644 --- a/hypervisor/include/arch/x86/cpu.h +++ b/hypervisor/include/arch/x86/cpu.h @@ -41,80 +41,80 @@ /* Define page size */ #define CPU_PAGE_SHIFT 12 #define CPU_PAGE_SIZE 0x1000 -#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000 +#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL #define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT #define MMU_PDE_PAGE_SHIFT 21 /* Define CPU stack alignment */ -#define CPU_STACK_ALIGN 16 +#define CPU_STACK_ALIGN 16UL /* CR0 register definitions */ -#define CR0_PG (1<<31) /* paging enable */ -#define CR0_CD (1<<30) /* cache disable */ -#define CR0_NW (1<<29) /* not write through */ -#define CR0_AM (1<<18) /* alignment mask */ -#define CR0_WP (1<<16) /* write protect */ -#define CR0_NE (1<<5) /* numeric error */ -#define CR0_ET (1<<4) /* extension type */ -#define CR0_TS (1<<3) /* task switched */ -#define CR0_EM (1<<2) /* emulation */ -#define CR0_MP (1<<1) /* monitor coprocessor */ -#define CR0_PE (1<<0) /* protected mode enabled */ +#define CR0_PG (1U<<31) /* paging enable */ +#define CR0_CD (1U<<30) /* cache disable */ +#define CR0_NW (1U<<29) /* not write through */ +#define CR0_AM (1U<<18) /* alignment mask */ +#define CR0_WP (1U<<16) /* write protect */ +#define CR0_NE (1U<<5) /* numeric error */ +#define CR0_ET (1U<<4) /* extension type */ +#define CR0_TS (1U<<3) /* task switched */ +#define CR0_EM (1U<<2) /* emulation */ +#define CR0_MP (1U<<1) /* monitor coprocessor */ +#define CR0_PE (1U<<0) /* protected mode enabled */ /* CR3 register definitions */ -#define CR3_PWT (1<<3) /* page-level write through */ -#define CR3_PCD (1<<4) /* page-level cache disable */ +#define CR3_PWT (1U<<3) /* page-level write through */ +#define CR3_PCD (1U<<4) /* page-level cache disable */ /* CR4 register definitions */ -#define CR4_VME (1<<0) /* virtual 8086 mode extensions */ -#define CR4_PVI (1<<1) /* protected mode virtual interrupts */ -#define CR4_TSD (1<<2) /* time stamp disable */ -#define CR4_DE (1<<3) /* debugging extensions */ -#define CR4_PSE (1<<4) /* page size extensions */ -#define CR4_PAE (1<<5) /* physical address extensions */ -#define CR4_MCE (1<<6) /* machine check enable */ -#define CR4_PGE (1<<7) /* page global enable */ -#define CR4_PCE (1<<8) +#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */ +#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */ +#define CR4_TSD (1U<<2) /* time stamp disable */ +#define CR4_DE (1U<<3) /* debugging extensions */ +#define CR4_PSE (1U<<4) /* page size extensions */ +#define CR4_PAE (1U<<5) /* physical address extensions */ +#define CR4_MCE (1U<<6) /* machine check enable */ +#define CR4_PGE (1U<<7) /* page global enable */ +#define CR4_PCE (1U<<8) /* performance monitoring counter enable */ -#define CR4_OSFXSR (1<<9) /* OS support for FXSAVE/FXRSTOR */ -#define CR4_OSXMMEXCPT (1<<10) +#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */ +#define CR4_OSXMMEXCPT (1U<<10) /* OS support for unmasked SIMD floating point exceptions */ -#define CR4_VMXE (1<<13) /* VMX enable */ -#define CR4_SMXE (1<<14) /* SMX enable */ -#define CR4_PCIDE (1<<17) /* PCID enable */ -#define CR4_OSXSAVE (1<<18) -#define CR4_SMEP (1<<20) -#define CR4_SMAP (1<<21) +#define CR4_VMXE (1U<<13) /* VMX enable */ +#define CR4_SMXE (1U<<14) /* SMX enable */ +#define CR4_PCIDE (1U<<17) /* PCID enable */ +#define CR4_OSXSAVE (1U<<18) +#define CR4_SMEP (1U<<20) +#define CR4_SMAP (1U<<21) /* XSAVE and Processor Extended States enable bit */ /* * Entries in the Interrupt Descriptor Table (IDT) */ -#define IDT_DE 0 /* #DE: Divide Error */ -#define IDT_DB 1 /* #DB: Debug */ -#define IDT_NMI 2 /* Nonmaskable External Interrupt */ -#define IDT_BP 3 /* #BP: Breakpoint */ -#define IDT_OF 4 /* #OF: Overflow */ -#define IDT_BR 5 /* #BR: Bound Range Exceeded */ -#define IDT_UD 6 /* #UD: Undefined/Invalid Opcode */ -#define IDT_NM 7 /* #NM: No Math Coprocessor */ -#define IDT_DF 8 /* #DF: Double Fault */ -#define IDT_FPUGP 9 /* Coprocessor Segment Overrun */ -#define IDT_TS 10 /* #TS: Invalid TSS */ -#define IDT_NP 11 /* #NP: Segment Not Present */ -#define IDT_SS 12 /* #SS: Stack Segment Fault */ -#define IDT_GP 13 /* #GP: General Protection Fault */ -#define IDT_PF 14 /* #PF: Page Fault */ -#define IDT_MF 16 /* #MF: FPU Floating-Point Error */ -#define IDT_AC 17 /* #AC: Alignment Check */ -#define IDT_MC 18 /* #MC: Machine Check */ -#define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */ -#define IDT_VE 20 /* #VE: Virtualization Exception */ +#define IDT_DE 0U /* #DE: Divide Error */ +#define IDT_DB 1U /* #DB: Debug */ +#define IDT_NMI 2U /* Nonmaskable External Interrupt */ +#define IDT_BP 3U /* #BP: Breakpoint */ +#define IDT_OF 4U /* #OF: Overflow */ +#define IDT_BR 5U /* #BR: Bound Range Exceeded */ +#define IDT_UD 6U /* #UD: Undefined/Invalid Opcode */ +#define IDT_NM 7U /* #NM: No Math Coprocessor */ +#define IDT_DF 8U /* #DF: Double Fault */ +#define IDT_FPUGP 9U /* Coprocessor Segment Overrun */ +#define IDT_TS 10U /* #TS: Invalid TSS */ +#define IDT_NP 11U /* #NP: Segment Not Present */ +#define IDT_SS 12U /* #SS: Stack Segment Fault */ +#define IDT_GP 13U /* #GP: General Protection Fault */ +#define IDT_PF 14U /* #PF: Page Fault */ +#define IDT_MF 16U /* #MF: FPU Floating-Point Error */ +#define IDT_AC 17U /* #AC: Alignment Check */ +#define IDT_MC 18U /* #MC: Machine Check */ +#define IDT_XF 19U /* #XF: SIMD Floating-Point Exception */ +#define IDT_VE 20U /* #VE: Virtualization Exception */ /*Bits in EFER special registers */ -#define EFER_LMA 0x000000400 /* Long mode active (R) */ +#define EFER_LMA 0x00000400U /* Long mode active (R) */ /* CPU clock frequencies (FSB) */ #define CPU_FSB_83KHZ 83200 @@ -140,7 +140,7 @@ #define CPU_STATE_DEAD 4 /* hypervisor stack bottom magic('intl') */ -#define SP_BOTTOM_MAGIC 0x696e746c +#define SP_BOTTOM_MAGIC 0x696e746cUL /* type of speculation control * 0 - no speculation control support @@ -310,7 +310,7 @@ void start_cpus(); /* This macro writes the stack pointer. */ #define CPU_SP_WRITE(stack_ptr) \ { \ - uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1); \ + uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1UL); \ asm volatile ("movq %0, %%rsp" : : "r"(rsp)); \ } diff --git a/hypervisor/include/arch/x86/cpuid.h b/hypervisor/include/arch/x86/cpuid.h index a9c3a1596..a31ae2b9d 100644 --- a/hypervisor/include/arch/x86/cpuid.h +++ b/hypervisor/include/arch/x86/cpuid.h @@ -15,73 +15,73 @@ #define CPUID_H_ /* CPUID bit definitions */ -#define CPUID_ECX_SSE3 (1<<0) -#define CPUID_ECX_PCLMUL (1<<1) -#define CPUID_ECX_DTES64 (1<<2) -#define CPUID_ECX_MONITOR (1<<3) -#define CPUID_ECX_DS_CPL (1<<4) -#define CPUID_ECX_VMX (1<<5) -#define CPUID_ECX_SMX (1<<6) -#define CPUID_ECX_EST (1<<7) -#define CPUID_ECX_TM2 (1<<8) -#define CPUID_ECX_SSSE3 (1<<9) -#define CPUID_ECX_CID (1<<10) -#define CPUID_ECX_FMA (1<<12) -#define CPUID_ECX_CX16 (1<<13) -#define CPUID_ECX_ETPRD (1<<14) -#define CPUID_ECX_PDCM (1<<15) -#define CPUID_ECX_DCA (1<<18) -#define CPUID_ECX_SSE4_1 (1<<19) -#define CPUID_ECX_SSE4_2 (1<<20) -#define CPUID_ECX_x2APIC (1<<21) -#define CPUID_ECX_MOVBE (1<<22) -#define CPUID_ECX_POPCNT (1<<23) -#define CPUID_ECX_AES (1<<25) -#define CPUID_ECX_XSAVE (1<<26) -#define CPUID_ECX_OSXSAVE (1<<27) -#define CPUID_ECX_AVX (1<<28) -#define CPUID_EDX_FPU (1<<0) -#define CPUID_EDX_VME (1<<1) -#define CPUID_EDX_DE (1<<2) -#define CPUID_EDX_PSE (1<<3) -#define CPUID_EDX_TSC (1<<4) -#define CPUID_EDX_MSR (1<<5) -#define CPUID_EDX_PAE (1<<6) -#define CPUID_EDX_MCE (1<<7) -#define CPUID_EDX_CX8 (1<<8) -#define CPUID_EDX_APIC (1<<9) -#define CPUID_EDX_SEP (1<<11) -#define CPUID_EDX_MTRR (1<<12) -#define CPUID_EDX_PGE (1<<13) -#define CPUID_EDX_MCA (1<<14) -#define CPUID_EDX_CMOV (1<<15) -#define CPUID_EDX_PAT (1<<16) -#define CPUID_EDX_PSE36 (1<<17) -#define CPUID_EDX_PSN (1<<18) -#define CPUID_EDX_CLF (1<<19) -#define CPUID_EDX_DTES (1<<21) -#define CPUID_EDX_ACPI (1<<22) -#define CPUID_EDX_MMX (1<<23) -#define CPUID_EDX_FXSR (1<<24) -#define CPUID_EDX_SSE (1<<25) -#define CPUID_EDX_SSE2 (1<<26) -#define CPUID_EDX_SS (1<<27) -#define CPUID_EDX_HTT (1<<28) -#define CPUID_EDX_TM1 (1<<29) -#define CPUID_EDX_IA64 (1<<30) -#define CPUID_EDX_PBE (1<<31) +#define CPUID_ECX_SSE3 (1UL<<0) +#define CPUID_ECX_PCLMUL (1UL<<1) +#define CPUID_ECX_DTES64 (1UL<<2) +#define CPUID_ECX_MONITOR (1UL<<3) +#define CPUID_ECX_DS_CPL (1UL<<4) +#define CPUID_ECX_VMX (1UL<<5) +#define CPUID_ECX_SMX (1UL<<6) +#define CPUID_ECX_EST (1UL<<7) +#define CPUID_ECX_TM2 (1UL<<8) +#define CPUID_ECX_SSSE3 (1UL<<9) +#define CPUID_ECX_CID (1UL<<10) +#define CPUID_ECX_FMA (1UL<<12) +#define CPUID_ECX_CX16 (1UL<<13) +#define CPUID_ECX_ETPRD (1UL<<14) +#define CPUID_ECX_PDCM (1UL<<15) +#define CPUID_ECX_DCA (1UL<<18) +#define CPUID_ECX_SSE4_1 (1UL<<19) +#define CPUID_ECX_SSE4_2 (1UL<<20) +#define CPUID_ECX_x2APIC (1UL<<21) +#define CPUID_ECX_MOVBE (1UL<<22) +#define CPUID_ECX_POPCNT (1UL<<23) +#define CPUID_ECX_AES (1UL<<25) +#define CPUID_ECX_XSAVE (1UL<<26) +#define CPUID_ECX_OSXSAVE (1UL<<27) +#define CPUID_ECX_AVX (1UL<<28) +#define CPUID_EDX_FPU (1UL<<0) +#define CPUID_EDX_VME (1UL<<1) +#define CPUID_EDX_DE (1UL<<2) +#define CPUID_EDX_PSE (1UL<<3) +#define CPUID_EDX_TSC (1UL<<4) +#define CPUID_EDX_MSR (1UL<<5) +#define CPUID_EDX_PAE (1UL<<6) +#define CPUID_EDX_MCE (1UL<<7) +#define CPUID_EDX_CX8 (1UL<<8) +#define CPUID_EDX_APIC (1UL<<9) +#define CPUID_EDX_SEP (1UL<<11) +#define CPUID_EDX_MTRR (1UL<<12) +#define CPUID_EDX_PGE (1UL<<13) +#define CPUID_EDX_MCA (1UL<<14) +#define CPUID_EDX_CMOV (1UL<<15) +#define CPUID_EDX_PAT (1UL<<16) +#define CPUID_EDX_PSE36 (1UL<<17) +#define CPUID_EDX_PSN (1UL<<18) +#define CPUID_EDX_CLF (1UL<<19) +#define CPUID_EDX_DTES (1UL<<21) +#define CPUID_EDX_ACPI (1UL<<22) +#define CPUID_EDX_MMX (1UL<<23) +#define CPUID_EDX_FXSR (1UL<<24) +#define CPUID_EDX_SSE (1UL<<25) +#define CPUID_EDX_SSE2 (1UL<<26) +#define CPUID_EDX_SS (1UL<<27) +#define CPUID_EDX_HTT (1UL<<28) +#define CPUID_EDX_TM1 (1UL<<29) +#define CPUID_EDX_IA64 (1UL<<30) +#define CPUID_EDX_PBE (1UL<<31) /* CPUID.07H:EBX.TSC_ADJUST*/ -#define CPUID_EBX_TSC_ADJ (1<<1) +#define CPUID_EBX_TSC_ADJ (1UL<<1) /* CPUID.07H:EDX.IBRS_IBPB*/ -#define CPUID_EDX_IBRS_IBPB (1<<26) +#define CPUID_EDX_IBRS_IBPB (1UL<<26) /* CPUID.07H:EDX.STIBP*/ -#define CPUID_EDX_STIBP (1<<27) +#define CPUID_EDX_STIBP (1UL<<27) /* CPUID.80000001H:EDX.Page1GB*/ -#define CPUID_EDX_PAGE1GB (1<<26) +#define CPUID_EDX_PAGE1GB (1UL<<26) /* CPUID.07H:EBX.INVPCID*/ -#define CPUID_EBX_INVPCID (1<<10) +#define CPUID_EBX_INVPCID (1UL<<10) /* CPUID.01H:ECX.PCID*/ -#define CPUID_ECX_PCID (1<<17) +#define CPUID_ECX_PCID (1UL<<17) /* CPUID source operands */ #define CPUID_VENDORSTRING 0