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fix "Procedure is not pure assembler"

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Misra C reqires assembly code should comply with
the rules list below:
  The assembly code's functionality should match the function's
name.If not,pls encapsulate the assembly code and give a suitable
name for describing the functionality.
V1->V2:
    1.remove the dead code
    2.update detail comment

V2->V3:
    1.replace the macro name with upper case.
    2.remove the typedef and rename the struct name
"_descriptor_table_" to "descriptor_table".

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
2018-11-06 10:05:19 +08:00
committed by lijinxia
parent 91fb441d7a
commit 7bb09f75da
9 changed files with 96 additions and 59 deletions
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52
hypervisor/include/arch/x86/cpu.h
View File

@@ -264,6 +264,11 @@ extern spinlock_t trampoline_spinlock;
*/
#define BROADCAST_CPU_ID 0xfffeU
struct descriptor_table {
uint16_t limit;
uint64_t base;
} __attribute__((packed));
/* CPU states defined */
enum pcpu_boot_state {
PCPU_STATE_RESET = 0U,
@@ -326,6 +331,11 @@ void stop_cpus(void);
void wait_sync_change(uint64_t *sync, uint64_t wake_sync);
void cpu_l1d_flush(void);
#define CPU_SEG_WRITE(seg, value16) \
{ \
asm volatile ("mov %%" STRINGIFY(seg) ", %%ax": "=a" (value16)); \
}
/* Read control register */
#define CPU_CR_READ(cr, result_ptr) \
{ \
@@ -341,6 +351,20 @@ void cpu_l1d_flush(void);
: "r"(value)); \
}
static inline uint64_t sgdt(void)
{
struct descriptor_table gdtb = {0U, 0UL};
asm volatile ("sgdt %0":"=m"(gdtb)::"memory");
return gdtb.base;
}
static inline uint64_t sidt(void)
{
struct descriptor_table idtb = {0U, 0UL};
asm volatile ("sidt %0":"=m"(idtb)::"memory");
return idtb.base;
}
/* Read MSR */
static inline void cpu_msr_read(uint32_t reg, uint64_t *msr_val_ptr)
{
@@ -360,6 +384,16 @@ static inline void cpu_msr_write(uint32_t reg, uint64_t msr_val)
asm volatile (" wrmsr " : : "c" (reg), "a" (msrl), "d" (msrh));
}
static inline void pause_cpu(void)
{
asm volatile ("pause" ::: "memory");
}
static inline void hlt_cpu(void)
{
asm volatile ("hlt");
}
#ifdef CONFIG_PARTITION_MODE
#define CPU_IRQ_DISABLE()
#else
@@ -388,22 +422,10 @@ static inline void cpu_sp_write(uint64_t *stack_ptr)
asm volatile ("movq %0, %%rsp" : : "r"(rsp));
}
/* Synchronizes all read accesses from memory */
#define CPU_MEMORY_READ_BARRIER() \
{ \
asm volatile ("lfence\n" : : : "memory"); \
}
/* Synchronizes all write accesses to memory */
#define CPU_MEMORY_WRITE_BARRIER() \
{ \
asm volatile ("sfence\n" : : : "memory"); \
}
/* Synchronizes all read and write accesses to/from memory */
#define CPU_MEMORY_BARRIER() \
{ \
asm volatile ("mfence\n" : : : "memory"); \
static inline void cpu_memory_barrier(void)
{
asm volatile ("mfence\n" : : : "memory");
}
/* Write the task register */

4
hypervisor/include/arch/x86/vmx.h
View File

@@ -477,10 +477,6 @@ static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
!= 0UL);
}
typedef struct _descriptor_table_{
uint16_t limit;
uint64_t base;
}__attribute__((packed)) descriptor_table;
#endif /* ASSEMBLER */
#endif /* VMX_H_ */