From 7bf78b7e429aeec2059aaee411eebbe250cc7222 Mon Sep 17 00:00:00 2001
From: "Li, Fei1" <fei1.li@intel.com>
Date: Mon, 17 Dec 2018 22:21:58 +0800
Subject: [PATCH] hv: add fast string enhanced rep movsb/stosb check on initial

The ACRN suppose the CPU support fast string enhanced rep.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
---
 hypervisor/arch/x86/cpu.c                 | 23 +++++++++++++++++++++++
 hypervisor/include/arch/x86/cpufeatures.h |  1 +
 hypervisor/include/arch/x86/msr.h         |  3 +++
 3 files changed, 27 insertions(+)

diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c
index 76b3e338f..176494d68 100644
--- a/hypervisor/arch/x86/cpu.c
+++ b/hypervisor/arch/x86/cpu.c
@@ -78,6 +78,24 @@ static inline bool get_monitor_cap(void)
 	return false;
 }
 
+static inline bool is_fast_string_erms_supported_and_enabled(void)
+{
+	bool ret = false;
+	uint32_t misc_enable = (uint32_t)msr_read(MSR_IA32_MISC_ENABLE);
+
+	if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0U) {
+		pr_fatal("%s, fast string is not enabled\n", __func__);
+	} else {
+		if (!cpu_has_cap(X86_FEATURE_ERMS)) {
+			pr_fatal("%s, enhanced rep movsb/stosb not supported\n", __func__);
+		} else {
+			ret = true;
+		}
+	}
+
+	return ret;
+}
+
 static uint64_t get_address_mask(uint8_t limit)
 {
 	return ((1UL << limit) - 1UL) & PAGE_MASK;
@@ -222,6 +240,11 @@ static int32_t hardware_detect_support(void)
 		return -ENODEV;
 	}
 
+	if (!is_fast_string_erms_supported_and_enabled()) {
+		return -ENODEV;
+	}
+
+
 	if (!cpu_has_vmx_unrestricted_guest_cap()) {
 		pr_fatal("%s, unrestricted guest not supported\n", __func__);
 		return -ENODEV;
diff --git a/hypervisor/include/arch/x86/cpufeatures.h b/hypervisor/include/arch/x86/cpufeatures.h
index 582a1026d..c00cca9db 100644
--- a/hypervisor/include/arch/x86/cpufeatures.h
+++ b/hypervisor/include/arch/x86/cpufeatures.h
@@ -71,6 +71,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
 #define X86_FEATURE_TSC_ADJ	((FEAT_7_0_EBX << 5U) +  1U)
 #define X86_FEATURE_SMEP	((FEAT_7_0_EBX << 5U) +  7U)
+#define X86_FEATURE_ERMS	((FEAT_7_0_EBX << 5U) +  9U)
 #define X86_FEATURE_INVPCID	((FEAT_7_0_EBX << 5U) + 10U)
 #define X86_FEATURE_SMAP	((FEAT_7_0_EBX << 5U) + 20U)
 
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index 2d94f9212..61484ce63 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -402,6 +402,9 @@
 #define PAT_MEM_TYPE_WB				0x06UL	/* writeback */
 #define PAT_MEM_TYPE_UCM			0x07UL	/* uncached minus */
 
+/* MISC_ENABLE bits: architectural */
+#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1U << 0U)
+
 #ifndef ASSEMBLER
 static inline bool pat_mem_type_invalid(uint64_t x)
 {