refine in cpu_caps.c

- we should not use print function before tsc setup
- is_ept_supported is internal API
- add is_apicv_supported to check apicv feature
- rename some functions to verb+obj format or better name

Changes to be committed:
	modified:   arch/x86/cpu.c
	modified:   arch/x86/cpu_caps.c
	modified:   include/arch/x86/cpu_caps.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>

hypervisor/arch/x86/cpu.c

@@ -102,9 +102,9 @@ void init_cpu_pre(uint16_t pcpu_id)
 		/* Get CPU capabilities thru CPUID, including the physical address bit
 		 * limit which is required for initializing paging.
 		 */
-		get_cpu_capabilities();
+		init_cpu_capabilities();
 
-		get_cpu_name();
+		init_cpu_model_name();
 
 		load_cpu_state_data();
 
@@ -116,7 +116,7 @@ void init_cpu_pre(uint16_t pcpu_id)
 			panic("x2APIC is not present!");
 		}
 
-		cpu_cap_detect();
+		detect_cpu_cap();
 
 		early_init_lapic();
 
@@ -174,12 +174,12 @@ void init_cpu_post(uint16_t pcpu_id)
 
 		pr_dbg("Core %hu is up", BOOT_CPU_ID);
 
-		if (hardware_detect_support() != 0) {
+		if (detect_hardware_support() != 0) {
 			panic("hardware not support!");
 		}
 
 		/* Warn for security feature not ready */
-		if (!check_cpu_security_config()) {
+		if (!check_cpu_security_cap()) {
 			pr_fatal("SECURITY WARNING!!!!!!");
 			pr_fatal("Please apply the latest CPU uCode patch!");
 		}

hypervisor/arch/x86/cpu_caps.c

@@ -93,7 +93,7 @@ static uint64_t get_address_mask(uint8_t limit)
 	return ((1UL << limit) - 1UL) & PAGE_MASK;
 }
 
-void get_cpu_capabilities(void)
+void init_cpu_capabilities(void)
 {
 	uint32_t eax, unused;
 	uint32_t family, model;
@@ -184,7 +184,7 @@ static bool is_ctrl_setting_allowed(uint64_t msr_val, uint32_t ctrl)
 	return ((((uint32_t)(msr_val >> 32UL)) & ctrl) == ctrl);
 }
 
-static void ept_cap_detect(void)
+static void detect_ept_cap(void)
 {
 	uint64_t msr_val;
 
@@ -216,25 +216,22 @@ static void ept_cap_detect(void)
 	}
 }
 
-static void apicv_cap_detect(void)
+static void detect_apicv_cap(void)
 {
 	uint8_t features;
 	uint64_t msr_val;
 
 	msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS);
 	if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS_TPR_SHADOW)) {
-		pr_fatal("APICv: No APIC TPR virtualization support.");
 		return;
 	}
 
 	msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2);
 	if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS2_VAPIC)) {
-		pr_fatal("APICv: No APIC-access virtualization support.");
 		return;
 	}
 
 	if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS2_VAPIC_REGS)) {
-		pr_fatal("APICv: No APIC-register virtualization support.");
 		return;
 	}
 
@@ -258,7 +255,7 @@ static void apicv_cap_detect(void)
 	cpu_caps.apicv_features = features;
 }
 
-static void vmx_mmu_cap_detect(void)
+static void detect_vmx_mmu_cap(void)
 {
 	uint64_t val;
 
@@ -268,18 +265,23 @@ static void vmx_mmu_cap_detect(void)
 	cpu_caps.vmx_vpid = (uint32_t) (val >> 32U);
 }
 
-void cpu_cap_detect(void)
+void detect_cpu_cap(void)
 {
-	apicv_cap_detect();
-	ept_cap_detect();
-	vmx_mmu_cap_detect();
+	detect_apicv_cap();
+	detect_ept_cap();
+	detect_vmx_mmu_cap();
 }
 
-bool is_ept_supported(void)
+static bool is_ept_supported(void)
 {
 	return (cpu_caps.ept_features != 0U);
 }
 
+static bool is_apicv_supported(void)
+{
+	return (cpu_caps.apicv_features != 0U);
+}
+
 bool is_apicv_reg_virtualization_supported(void)
 {
 	return ((cpu_caps.apicv_features & VAPIC_FEATURE_VIRT_REG) != 0U);
@@ -305,7 +307,7 @@ bool cpu_has_vmx_vpid_cap(uint32_t bit_mask)
 	return ((cpu_caps.vmx_vpid & bit_mask) != 0U);
 }
 
-void get_cpu_name(void)
+void init_cpu_model_name(void)
 {
 	cpuid(CPUID_EXTEND_FUNCTION_2,
 		(uint32_t *)(boot_cpu_data.model_name),
@@ -326,7 +328,7 @@ void get_cpu_name(void)
 	boot_cpu_data.model_name[48] = '\0';
 }
 
-bool check_cpu_security_config(void)
+bool check_cpu_security_cap(void)
 {
 	if (cpu_has_cap(X86_FEATURE_ARCH_CAP)) {
 		x86_arch_capabilities = msr_read(MSR_IA32_ARCH_CAPABILITIES);
@@ -412,7 +414,7 @@ static int32_t check_vmx_mmu_cap(void)
  * we should supplement which feature/capability we must support
  * here later.
  */
-int32_t hardware_detect_support(void)
+int32_t detect_hardware_support(void)
 {
 	int32_t ret;
 
@@ -481,6 +483,10 @@ int32_t hardware_detect_support(void)
 		return -ENODEV;
 	}
 
+	if (!is_apicv_supported()) {
+		pr_fatal("%s, APICV not supported\n", __func__);
+	}
+
 	if (boot_cpu_data.cpuid_level < 0x15U) {
 		pr_fatal("%s, required CPU feature not supported\n", __func__);
 		return -ENODEV;

hypervisor/include/arch/x86/cpu_caps.h

@@ -63,16 +63,15 @@ bool has_monitor_cap(void);
 bool is_apicv_reg_virtualization_supported(void);
 bool is_apicv_intr_delivery_supported(void);
 bool is_apicv_posted_intr_supported(void);
-bool is_ept_supported(void);
 bool cpu_has_cap(uint32_t bit);
 bool cpu_has_vmx_ept_cap(uint32_t bit_mask);
 bool cpu_has_vmx_vpid_cap(uint32_t bit_mask);
-void get_cpu_capabilities(void);
-void get_cpu_name(void);
-void cpu_cap_detect(void);
-bool check_cpu_security_config(void);
+void init_cpu_capabilities(void);
+void init_cpu_model_name(void);
+void detect_cpu_cap(void);
+bool check_cpu_security_cap(void);
 void cpu_l1d_flush(void);
-int hardware_detect_support(void);
+int detect_hardware_support(void);
 
 #endif /* ASSEMBLER */