github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-18 19:57:31 +00:00
Code Issues Projects Releases Wiki Activity

acrn-config: add MAX_CACHE_CLOS_NUM_ENTRIES/MAX_MBA_CLOS_NUM_ENTRIES macros

Browse Source 
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.

 MAX_MBA_CLOS_NUM_ENTRIES:
  Max number of Cache Mask entries corresponding to each CLOS.
  This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
  cache mask values for Data and Code when CDP is enabled.

 MAX_CACHE_CLOS_NUM_ENTRIES:
  Max number of MBA delay entries corresponding to each CLOS.

2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.

Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
Wei Liu 2020-08-23 17:05:46 -07:00 committed by wenlingz
parent a425730f64
commit 7eb103478a
7 changed files with 60 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
misc/acrn-config/board_config/board_c.py
View File

@ -103,7 +103,7 @@ def populate_clos_mask_msr(rdt_res, cat_mask_list, config):
idx = 0
for cat_mask in cat_mask_list:
print("\t{", file=config)
print("\t\t.clos_mask = CLOS_MASK_{},".format(idx), file=config)
print("\t\t.value.clos_mask = CLOS_MASK_{},".format(idx), file=config)
print("\t\t.msr_index = MSR_IA32_{0}_MASK_BASE + {1},".format(
rdt_res, idx), file=config)
print("\t},", file=config)
@ -119,7 +119,7 @@ def populate_mba_delay_mask(rdt_res, mba_delay_list, config):
idx = 0
for mba_delay_mask in mba_delay_list:
print("\t{", file=config)
print("\t\t.mba_delay = MBA_MASK_{},".format(idx), file=config)
print("\t\t.value.mba_delay = MBA_MASK_{},".format(idx), file=config)
print("\t\t.msr_index = MSR_IA32_{0}_MASK_BASE + {1},".format(
rdt_res, idx), file=config)
print("\t},", file=config)
@ -139,8 +139,6 @@ def gen_rdt_res(config):
cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")
# TODO: Since use the HV_SUPPORTED_MAX_CLOS for L2/L3/MBA, so use the minimal number of them
common_clos_max = min(len(cat_mask_list), len(mba_delay_list))
if common_clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\
common_clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE:
@ -149,29 +147,29 @@ def gen_rdt_res(config):
print("\n#ifdef CONFIG_RDT_ENABLED", file=config)
if len(rdt_resources) == 0 or common_clos_max == 0:
print("struct platform_clos_info platform_{0}_clos_array[HV_SUPPORTED_MAX_CLOS];".format("l2"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[HV_SUPPORTED_MAX_CLOS];".format("l3"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[HV_SUPPORTED_MAX_CLOS];".format("mba"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];".format("l2"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];".format("l3"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];".format("mba"), file=config)
else:
for idx, rdt_res in enumerate(rdt_resources):
if rdt_res == "L2":
rdt_res_str = "l2"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"HV_SUPPORTED_MAX_CLOS"), file=config)
"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
populate_clos_mask_msr(rdt_res, cat_mask_list, config)
print("};\n", file=config)
res_present[RDT.L2.value] = 1
elif rdt_res == "L3":
rdt_res_str = "l3"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"HV_SUPPORTED_MAX_CLOS"), file=config)
"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
populate_clos_mask_msr(rdt_res, cat_mask_list, config)
print("};\n", file=config)
res_present[RDT.L3.value] = 1
elif rdt_res == "MBA":
rdt_res_str = "mba"
print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
"HV_SUPPORTED_MAX_CLOS"), file=config)
"MAX_MBA_CLOS_NUM_ENTRIES"), file=config)
err_dic = populate_mba_delay_mask(rdt_res, mba_delay_list, config)
print("};\n", file=config)
res_present[RDT.MBA.value] = 1
@ -180,11 +178,11 @@ def gen_rdt_res(config):
return err_dic
if res_present[RDT.L2.value] == 0:
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l2", "HV_SUPPORTED_MAX_CLOS"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l2", "MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
if res_present[RDT.L3.value] == 0:
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l3", "HV_SUPPORTED_MAX_CLOS"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l3", "MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
if res_present[RDT.MBA.value] == 0:
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("mba", "HV_SUPPORTED_MAX_CLOS"), file=config)
print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("mba", "MAX_MBA_CLOS_NUM_ENTRIES"), file=config)
print("#endif", file=config)

5
misc/acrn-config/board_config/board_info_h.py
View File

@ -71,17 +71,12 @@ def generate_file(config):
cpu_list = board_cfg_lib.get_processor_info()
max_cpu_num = len(cpu_list)
# set macro of max clos number
common_clos_max = board_cfg_lib.get_common_clos_max()
max_mba_clos_entries = common_clos_max
# start to generate board_info.h
print("{0}".format(board_cfg_lib.HEADER_LICENSE), file=config)
print(BOARD_INFO_DEFINE, file=config)
# define CONFIG_MAX_PCPCU_NUM
print("#define MAX_PCPU_NUM\t\t\t{}U".format(max_cpu_num), file=config)
print("#define HV_SUPPORTED_MAX_CLOS\t\t{}U".format(common_clos_max), file=config)
# define MAX_VMSIX_ON_MSI_PDEVS_NUM
gen_known_caps_pci_head(config)

43
misc/acrn-config/board_config/misc_cfg_h.py
View File

@ -139,6 +139,16 @@ def parse_boot_info():
return (err_dic, sos_cmdlines, sos_rootfs, vuart0_dic, vuart1_dic)
def clos_per_vm_gen(config):
clos_per_vm = {}
clos_per_vm = common.get_leaf_tag_map(
common.SCENARIO_INFO_FILE, "clos", "vcpu_clos")
for i,clos_list_i in clos_per_vm.items():
clos_config = scenario_cfg_lib.clos_assignment(clos_per_vm, i)
print("#define VM{0}_VCPU_CLOS\t\t\t{1}".format(i, clos_config['clos_map']), file=config)
def generate_file(config):
"""
Start to generate board.c
@ -241,6 +251,34 @@ def generate_file(config):
sos_bootarg_diff(sos_cmdlines, config)
print("", file=config)
common_clos_max = board_cfg_lib.get_common_clos_max()
max_mba_clos_entries = common_clos_max
max_cache_clos_entries = common_clos_max
if board_cfg_lib.is_cdp_enabled():
max_cache_clos_entries_cdp_enable = 2 * common_clos_max
(res_info, rdt_res_clos_max, clos_max_mask_list) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
common_clos_max_cdp_disable = min(rdt_res_clos_max)
print("#ifdef CONFIG_RDT_ENABLED", file=config)
print("#ifdef CONFIG_CDP_ENABLED", file=config)
print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max), file=config)
print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries_cdp_enable), file=config)
print("#else", file=config)
print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max_cdp_disable), file=config)
print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries), file=config)
print("#endif", file=config)
print("#define MAX_MBA_CLOS_NUM_ENTRIES\t{}U".format(max_mba_clos_entries), file=config)
else:
print("#ifdef CONFIG_RDT_ENABLED", file=config)
print("#define HV_SUPPORTED_MAX_CLOS\t{}U".format(common_clos_max), file=config)
print("#define MAX_MBA_CLOS_NUM_ENTRIES\t{}U".format(max_mba_clos_entries), file=config)
print("#define MAX_CACHE_CLOS_NUM_ENTRIES\t{}U".format(max_cache_clos_entries), file=config)
if not board_cfg_lib.is_rdt_supported():
print("#endif", file=config)
print("", file=config)
if board_cfg_lib.is_rdt_supported():
(rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
@ -256,6 +294,10 @@ def generate_file(config):
idx += 1
print("", file=config)
clos_per_vm_gen(config)
print("#endif", file=config)
print("", file=config)
vm0_pre_launch = False
common.get_vm_types()
for vm_idx,vm_type in common.VM_TYPES.items():
@ -266,7 +308,6 @@ def generate_file(config):
print("#define VM0_PASSTHROUGH_TPM", file=config)
print("#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL", file=config)
print("#define VM0_TPM_BUFFER_SIZE 0x5000UL", file=config)
print("", file=config)
print("{}".format(MISC_CFG_END), file=config)

4
misc/acrn-config/library/hv_cfg_lib.py
View File

@ -182,7 +182,7 @@ def cat_max_mask_check(cat_mask_list, feature, cat_str, max_mask_str):
cat_max_mask_settings_len = len(cat_mask_list)
if clos_max_set_entry != cat_max_mask_settings_len:
key = 'hv,{},{},{}'.format(feature, cat_str, max_mask_str)
ERR_LIST[key] = "Number of Cache mask entries should be equal to HV_SUPPORTED_MAX_CLOS={}".format(clos_max_set_entry)
ERR_LIST[key] = "Number of Cache mask entries should be equal to MAX_CACHE_CLOS_NUM_ENTRIES={}".format(clos_max_set_entry)
return
clos_max_mask_str = clos_max_mask_list[0].strip('"').strip("'")
@ -212,7 +212,7 @@ def mba_delay_check(mba_delay_list, feature, mba_str, max_mask_str):
mba_delay_settings_len = len(mba_delay_list)
if clos_max != mba_delay_settings_len:
key = 'hv,{},{},{}'.format(feature, mba_str, max_mask_str)
ERR_LIST[key] = "Number of MBA delay entries should be equal to HV_SUPPORTED_MAX_CLOS={}".format(clos_max)
ERR_LIST[key] = "Number of MBA delay entries should be equal to MAX_MBA_CLOS_NUM_ENTRIES={}".format(clos_max)
return
mba_idx = res_info.index("MBA")

4
misc/acrn-config/scenario_config/vm_configurations_c.py
View File

@ -210,8 +210,10 @@ def clos_output(scenario_items, i, config):
"""
hv_info = scenario_items['hv']
if board_cfg_lib.is_rdt_supported() and hv_info.features.rdt_enabled == 'y':
if board_cfg_lib.is_rdt_supported():
print("#ifdef CONFIG_RDT_ENABLED", file=config)
print("\t\t.clos = VM{}_VCPU_CLOS,".format(i), file=config)
print("#endif", file=config)
def get_guest_flag(flags):
"""

16
misc/acrn-config/scenario_config/vm_configurations_h.py
View File

@ -40,19 +40,6 @@ def cpu_affinity_output(vm_info, i, config):
print("#define VM{0}_CONFIG_CPU_AFFINITY {1}".format(
i, cpu_bits['cpu_map']), file=config)
def clos_config_output(scenario_items, i, config):
"""
Output the macro vcpu affinity
:param scenario_items: the data structure have all the xml items values
:param i: the index of vm id
:param config: file pointor to store the information
"""
vm_info = scenario_items['vm']
hv_info = scenario_items['hv']
if board_cfg_lib.is_rdt_supported() and hv_info.features.rdt_enabled == 'y':
clos_config = vm_info.get_clos_bitmap(i)
print("#define VM{0}_VCPU_CLOS\t\t\t{1}".format(i, clos_config['clos_map']), file=config)
def scenario_vm_num(scenario_items, config):
@ -80,7 +67,6 @@ def gen_pre_launch_vm(scenario_items, config):
cpu_bits = vm_info.get_cpu_bitmap(vm_i)
cpu_affinity_output(vm_info, vm_i, config)
clos_config_output(scenario_items, vm_i, config)
print("#define VM{0}_CONFIG_MEM_START_HPA {1}UL".format(
vm_i, vm_info.mem_info.mem_start_hpa[vm_i]), file=config)
print("#define VM{0}_CONFIG_MEM_SIZE {1}UL".format(
@ -112,7 +98,6 @@ def gen_post_launch_header(scenario_items, config):
is_post_vm_available = True
cpu_affinity_output(vm_info, vm_i, config)
clos_config_output(scenario_items, vm_i, config)
if vm_info.shmem.shmem_enabled == 'y' and vm_i in vm_info.shmem.shmem_num.keys():
print("#define VM{}_CONFIG_PCI_DEV_NUM {}U".format(vm_i,
@ -141,7 +126,6 @@ def gen_sos_header(scenario_items, config):
for vm_i,vm_type in common.VM_TYPES.items():
if vm_type == 'SOS_VM':
cpu_affinity_output(vm_info, vm_i, config)
clos_config_output(scenario_items, vm_i, config)
print("", file=config)

2
misc/vm_configs/xmls/config-xmls/ehl-crb-b/industry.xml
View File

@ -117,10 +117,12 @@
<guest_flag>0</guest_flag>
</guest_flags>
<cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
<pcpu_id>0</pcpu_id>
<pcpu_id>1</pcpu_id>
</cpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section configurable="0" desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>