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doc: Fix links

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- Fix broken software.intel.com links that moved to intel.com domain

Signed-off-by: Reyes, Amy <amy.reyes@intel.com>
This commit is contained in:
Reyes, Amy 2022-04-14 16:12:07 -07:00 committed by David Kinder
parent df7826245e
commit 7f2175cdce
6 changed files with 18 additions and 20 deletions
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2
doc/developer-guides/asm_coding_guidelines.rst
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@ -838,4 +838,4 @@ sequence defined in System V Application Binary Interface AMD64 Architecture
Processor Supplement. Processor Supplement.
Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf>`_. Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://www.intel.com/content/dam/develop/external/us/en/documents/mpx-linux64-abi.pdf>`_.

6
doc/developer-guides/hld/hld-splitlock.rst
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@ -32,7 +32,7 @@ ways:
This atomic operation is called a Split-locked Access. For this situation, This atomic operation is called a Split-locked Access. For this situation,
the LOCK# bus signal is asserted to lock the system bus, to ensure the LOCK# bus signal is asserted to lock the system bus, to ensure
the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual(SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_. the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
Split-locked Access can cause unexpected long latency to ordinary memory Split-locked Access can cause unexpected long latency to ordinary memory
operations by other CPUs while the bus is locked. This degraded system operations by other CPUs while the bus is locked. This degraded system
@ -51,9 +51,7 @@ an opportunity to decide how to handle this instruction:
- It can allow the instruction to run with LOCK# bus signal potentially - It can allow the instruction to run with LOCK# bus signal potentially
impacting performance of other CPUs. impacting performance of other CPUs.
- It can disable LOCK# assertion for split locked access, but - It can disable LOCK# assertion for split locked access, but
improperly makes the instruction non-atomic. (Intel plans to remove this CPU feature improperly makes the instruction non-atomic.
from upcoming products as documented in
`SDM, Volume 1, (Section 2.4 PROPOSED REMOVAL FROM UPCOMING PRODUCTS.) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture>`_
- It can terminate the software at this instruction. - It can terminate the software at this instruction.
Feature Enumeration and Control Feature Enumeration and Control

2
doc/developer-guides/hld/hv-rdt.rst
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@ -11,7 +11,7 @@ resources, ACRN can optimize RTVM performance over regular VMs. In ACRN, the
CAT and MBA are configured via the "VM-Configuration". The resources CAT and MBA are configured via the "VM-Configuration". The resources
allocated for VMs are determined in the VM configuration (:ref:`rdt_vm_configuration`). allocated for VMs are determined in the VM configuration (:ref:`rdt_vm_configuration`).
For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_. For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
Objective of CAT Objective of CAT

10
doc/developer-guides/l1tf.rst
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@ -9,7 +9,7 @@ Overview
Refer to `Intel Analysis of L1TF`_ and `Linux L1TF document`_ for details. Refer to `Intel Analysis of L1TF`_ and `Linux L1TF document`_ for details.
.. _Intel Analysis of L1TF: .. _Intel Analysis of L1TF:
https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/l1-terminal-fault.html
.. _Linux L1TF document: .. _Linux L1TF document:
https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html
@ -130,15 +130,15 @@ providing necessary capability for VMM to use for further mitigation.
ACRN will check the platform capability based on `CPUID enumeration ACRN will check the platform capability based on `CPUID enumeration
and architectural MSR`_. For an L1TF affected platform (CPUID.07H.EDX.29 and architectural MSR`_. For an L1TF affected platform (CPUID.07H.EDX.29
with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability(CPUID.07H.EDX.28) with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability (CPUID.07H.EDX.28)
must be supported. must be supported.
.. _CPUID enumeration and architectural MSR: .. _CPUID enumeration and architectural MSR:
https://software.intel.com/security-software-guidance/insights/deep-dive-cpuid-enumeration-and-architectural-msrs https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html
Not all the mitigations below will be implemented in ACRN, and not all of Not all the mitigations below will be implemented in ACRN, and not all of
them apply to a specific ACRN deployment. Check the 'Mitigation Status'_ and them apply to a specific ACRN deployment. Check the `Mitigation Status`_ and
'Mitigation Recommendations'_ sections for guidance. `Mitigation Recommendations`_ sections for guidance.
L1D Flush on VMENTRY L1D Flush on VMENTRY
==================== ====================

8
doc/tutorials/rdt_configuration.rst
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@ -28,10 +28,10 @@ Steps #2 and #3 configure RDT resources for a VM and can be done in two ways:
The following sections discuss how to detect, enumerate capabilities, and The following sections discuss how to detect, enumerate capabilities, and
configure RDT resources for VMs in the ACRN hypervisor. configure RDT resources for VMs in the ACRN hypervisor.
For further details, refer to the ACRN RDT high-level design For further details, refer to the ACRN RDT high-level design :ref:`hv_rdt` and
:ref:`hv_rdt` and `Intel 64 and IA-32 Architectures Software Developer's `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3,
Manual, (Section 17.19 Intel Resource Director Technology Allocation Features) (Section 17.19 Intel Resource Director Technology Allocation Features)
<https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_ <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
.. _rdt_detection_capabilities: .. _rdt_detection_capabilities:

10
doc/tutorials/rtvm_performance_tips.rst
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@ -72,11 +72,11 @@ using LAPIC passthrough. A few exceptions exist:
- NMI - ACRN uses NMI for system-level notification. - NMI - ACRN uses NMI for system-level notification.
You should avoid VM-exits triggered by operations initiated by the You should avoid VM-exits triggered by operations initiated by the vCPU. Refer
vCPU. Refer to the `Intel Software Developer Manuals (SDM) to the `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM)
<https://software.intel.com/en-us/articles/intel-sdm>`_ "Instructions <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_
Cause VM-exits Unconditionally" (SDM V3, 25.1.2) and "Instructions That "Instructions That Cause VM Exits Unconditionally" (SDM V3, 25.1.2) and
Cause VM-exits Conditionally" (SDM V3, 25.1.3). "Instructions That Cause VM Exits Conditionally" (SDM V3, 25.1.3).
Tip: Do not use CPUID in a real-time critical section. Tip: Do not use CPUID in a real-time critical section.
The CPUID instruction causes VM-exits unconditionally. You should The CPUID instruction causes VM-exits unconditionally. You should