mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-17 19:27:28 +00:00
HV:CPU:Constant values replace with CPU MACRO
MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, all unsigned constants must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
This commit is contained in:
Xiangyang Wu
parent
d7f071200d
commit
7fd3c6245a
@ -59,7 +59,8 @@ vmx_vmrun:
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/* 0x00000048 = MSR_IA32_SPEC_CTRL */
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movl $0x00000048,%ecx
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mov CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rdi),%rax
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/*0xc0=192=PU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
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mov 0xc0(%rdi),%rax
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movl $0,%edx
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wrmsr
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@ -80,25 +81,43 @@ next:
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/* Compare the launch flag to see if launching (1) or resuming (0) */
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cmp $VM_LAUNCH, %rsi
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mov CPU_CONTEXT_OFFSET_CR2(%rdi),%rax
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/*128U=0x80=PU_CONTEXT_OFFSET_CR2*/
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mov 0x80(%rdi),%rax
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mov %rax,%cr2
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mov CPU_CONTEXT_OFFSET_RAX(%rdi),%rax
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mov CPU_CONTEXT_OFFSET_RBX(%rdi),%rbx
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mov CPU_CONTEXT_OFFSET_RCX(%rdi),%rcx
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mov CPU_CONTEXT_OFFSET_RDX(%rdi),%rdx
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mov CPU_CONTEXT_OFFSET_RBP(%rdi),%rbp
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mov CPU_CONTEXT_OFFSET_RSI(%rdi),%rsi
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mov CPU_CONTEXT_OFFSET_R8(%rdi),%r8
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mov CPU_CONTEXT_OFFSET_R9(%rdi),%r9
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mov CPU_CONTEXT_OFFSET_R10(%rdi),%r10
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mov CPU_CONTEXT_OFFSET_R11(%rdi),%r11
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mov CPU_CONTEXT_OFFSET_R12(%rdi),%r12
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mov CPU_CONTEXT_OFFSET_R13(%rdi),%r13
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mov CPU_CONTEXT_OFFSET_R14(%rdi),%r14
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mov CPU_CONTEXT_OFFSET_R15(%rdi),%r15
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/*
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* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
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* 8U=0x8=CPU_CONTEXT_OFFSET_RBX
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* 16U=0x10=CPU_CONTEXT_OFFSET_RCX
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* 24U=0x18=CPU_CONTEXT_OFFSET_RDX
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* 32U=0x20=CPU_CONTEXT_OFFSET_RBP
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* 40U=0x28=CPU_CONTEXT_OFFSET_RSI
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* 48U=0x30=CPU_CONTEXT_OFFSET_R8
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* 56U=0x38=CPU_CONTEXT_OFFSET_R9
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* 64U=0x40=CPU_CONTEXT_OFFSET_R10
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* 72U=0x48=CPU_CONTEXT_OFFSET_R11
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* 80U=0x50=CPU_CONTEXT_OFFSET_R12
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* 88U=0x58=CPU_CONTEXT_OFFSET_R13
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* 96U=0x60=CPU_CONTEXT_OFFSET_R14
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* 104U=0x68=CPU_CONTEXT_OFFSET_R15
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*/
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mov 0x0(%rdi),%rax
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mov 0x8(%rdi),%rbx
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mov 0x10(%rdi),%rcx
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mov 0x18(%rdi),%rdx
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mov 0x20(%rdi),%rbp
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mov 0x28(%rdi),%rsi
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mov 0x30(%rdi),%r8
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mov 0x38(%rdi),%r9
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mov 0x40(%rdi),%r10
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mov 0x48(%rdi),%r11
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mov 0x50(%rdi),%r12
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mov 0x58(%rdi),%r13
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mov 0x60(%rdi),%r14
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mov 0x68(%rdi),%r15
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mov CPU_CONTEXT_OFFSET_RDI(%rdi),%rdi
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/*112U=0x70=CPU_CONTEXT_OFFSET_RDI*/
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mov 0x70(%rdi),%rdi
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/* Execute appropriate VMX instruction */
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je vm_launch
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@ -121,31 +140,51 @@ vm_exit:
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save guest RDI in its place */
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xchg 0(%rsp),%rdi
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/* Save current GPRs to guest state area */
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mov %rax,CPU_CONTEXT_OFFSET_RAX(%rdi)
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/* Save current GPRs to guest state area;
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* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
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*/
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mov %rax,0x0(%rdi)
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mov %cr2,%rax
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mov %rax,CPU_CONTEXT_OFFSET_CR2(%rdi)
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/*128U=0x80=CPU_CONTEXT_OFFSET_CR2*/
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mov %rax,0x80(%rdi)
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mov %rbx,CPU_CONTEXT_OFFSET_RBX(%rdi)
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mov %rcx,CPU_CONTEXT_OFFSET_RCX(%rdi)
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mov %rdx,CPU_CONTEXT_OFFSET_RDX(%rdi)
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mov %rbp,CPU_CONTEXT_OFFSET_RBP(%rdi)
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mov %rsi,CPU_CONTEXT_OFFSET_RSI(%rdi)
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mov %r8,CPU_CONTEXT_OFFSET_R8(%rdi)
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mov %r9,CPU_CONTEXT_OFFSET_R9(%rdi)
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mov %r10,CPU_CONTEXT_OFFSET_R10(%rdi)
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mov %r11,CPU_CONTEXT_OFFSET_R11(%rdi)
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mov %r12,CPU_CONTEXT_OFFSET_R12(%rdi)
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mov %r13,CPU_CONTEXT_OFFSET_R13(%rdi)
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mov %r14,CPU_CONTEXT_OFFSET_R14(%rdi)
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mov %r15,CPU_CONTEXT_OFFSET_R15(%rdi)
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/*
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* 8U=0x8=CPU_CONTEXT_OFFSET_RBX
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* 16U=0x10=CPU_CONTEXT_OFFSET_RCX
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* 24U=0x18=CPU_CONTEXT_OFFSET_RDX
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* 32U=0x20=CPU_CONTEXT_OFFSET_RBP
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* 40U=0x28=CPU_CONTEXT_OFFSET_RSI
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* 48U=0x30=CPU_CONTEXT_OFFSET_R8
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* 56U=0x38=CPU_CONTEXT_OFFSET_R9
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* 64U=0x40=CPU_CONTEXT_OFFSET_R10
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* 72U=0x48=CPU_CONTEXT_OFFSET_R11
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* 80U=0x50=CPU_CONTEXT_OFFSET_R12
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* 88U=0x58=CPU_CONTEXT_OFFSET_R13
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* 96U=0x60=CPU_CONTEXT_OFFSET_R14
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* 104U=0x68=CPU_CONTEXT_OFFSET_R15
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*/
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mov %rbx,0x8(%rdi)
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mov %rcx,0x10(%rdi)
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mov %rdx,0x18(%rdi)
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mov %rbp,0x20(%rdi)
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mov %rsi,0x28(%rdi)
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mov %r8,0x30(%rdi)
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mov %r9,0x38(%rdi)
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mov %r10,0x40(%rdi)
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mov %r11,0x48(%rdi)
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mov %r12,0x50(%rdi)
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mov %r13,0x58(%rdi)
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mov %r14,0x60(%rdi)
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mov %r15,0x68(%rdi)
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/* Load guest RDI off host stack and into RDX */
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mov 0(%rsp),%rdx
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/* Save guest RDI to guest state area */
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mov %rdx,CPU_CONTEXT_OFFSET_RDI(%rdi)
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/* Save guest RDI to guest state area
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*112U=0x70=CPU_CONTEXT_OFFSET_RDI
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*/
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mov %rdx,0x70(%rdi)
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/* Save RDI to RSI for later SPEC_CTRL save*/
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mov %rdi,%rsi
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@ -192,7 +231,8 @@ vm_eval_error:
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/*192U=0xc0=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
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mov %rax,0xc0(%rsi)
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/* 0x1 = SPEC_ENABLE_IBRS */
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movl $0x1,%eax
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movl $0,%edx
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@ -215,7 +255,8 @@ ibrs_opt:
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/*192U=0xc0=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
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mov %rax,0xc0(%rsi)
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/* 0x2 = SPEC_ENABLE_STIBP */
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movl $0x2,%eax
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movl $0,%edx
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@ -5,6 +5,22 @@
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#include <vcpu.h>
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#include <spinlock.h>
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/* NOTE:
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*
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* MISRA C requires that all unsigned constants should have the suffix 'U'
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* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
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* example, binutils 2.26 fails to compile assembly in that case. To work this
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* around, all unsigned constants must be explicitly spells out in assembly
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* with a comment tracking the original expression from which the magic
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* number is calculated. As an example:
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*
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* /* 0x00000668 =
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* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
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* movl $0x00000668, %eax
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*
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* Make sure that these numbers are updated accordingly if the definition of
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* the macros involved are changed.
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*/
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.text
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.align 8
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.code64
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@ -16,43 +32,70 @@
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.global __enter_s3
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__enter_s3:
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movq %rax, CPU_CONTEXT_OFFSET_RAX + cpu_ctx(%rip)
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movq %rbx, CPU_CONTEXT_OFFSET_RBX + cpu_ctx(%rip)
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movq %rcx, CPU_CONTEXT_OFFSET_RCX + cpu_ctx(%rip)
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movq %rdx, CPU_CONTEXT_OFFSET_RDX + cpu_ctx(%rip)
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movq %rdi, CPU_CONTEXT_OFFSET_RDI + cpu_ctx(%rip)
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movq %rsi, CPU_CONTEXT_OFFSET_RSI + cpu_ctx(%rip)
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movq %rbp, CPU_CONTEXT_OFFSET_RBP + cpu_ctx(%rip)
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movq %rsp, CPU_CONTEXT_OFFSET_RSP + cpu_ctx(%rip)
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movq %r8, CPU_CONTEXT_OFFSET_R8 + cpu_ctx(%rip)
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movq %r9, CPU_CONTEXT_OFFSET_R9 + cpu_ctx(%rip)
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movq %r10, CPU_CONTEXT_OFFSET_R10 + cpu_ctx(%rip)
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movq %r11, CPU_CONTEXT_OFFSET_R11 + cpu_ctx(%rip)
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movq %r12, CPU_CONTEXT_OFFSET_R12 + cpu_ctx(%rip)
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movq %r13, CPU_CONTEXT_OFFSET_R13 + cpu_ctx(%rip)
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movq %r14, CPU_CONTEXT_OFFSET_R14 + cpu_ctx(%rip)
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movq %r15, CPU_CONTEXT_OFFSET_R15 + cpu_ctx(%rip)
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/*
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* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
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* 8U=0x8=CPU_CONTEXT_OFFSET_RBX
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* 16U=0x10=CPU_CONTEXT_OFFSET_RCX
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* 24U=0x18=CPU_CONTEXT_OFFSET_RDX
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* 112U=0x70=CPU_CONTEXT_OFFSET_RDI
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* 40U=0x28=CPU_CONTEXT_OFFSET_RSI
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* 32U=0x20=CPU_CONTEXT_OFFSET_RBP
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* 160=0xa0=CPU_CONTEXT_OFFSET_RSP
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* 48U=0x30=CPU_CONTEXT_OFFSET_R8
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* 56U=0x38=CPU_CONTEXT_OFFSET_R9
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* 64U=0x40=CPU_CONTEXT_OFFSET_R10
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* 72U=0x48=CPU_CONTEXT_OFFSET_R11
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* 80U=0x50=CPU_CONTEXT_OFFSET_R12
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* 88U=0x58=CPU_CONTEXT_OFFSET_R13
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* 96U=0x60=CPU_CONTEXT_OFFSET_R14
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* 104U=0x68=CPU_CONTEXT_OFFSET_R15
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*/
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movq %rax, 0x0 + cpu_ctx(%rip)
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movq %rbx, 0x8 + cpu_ctx(%rip)
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movq %rcx, 0x10 + cpu_ctx(%rip)
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movq %rdx, 0x18 + cpu_ctx(%rip)
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movq %rdi, 0x70 + cpu_ctx(%rip)
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movq %rsi, 0x28 + cpu_ctx(%rip)
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movq %rbp, 0x20 + cpu_ctx(%rip)
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movq %rsp, 0xa0 + cpu_ctx(%rip)
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movq %r8, 0x30 + cpu_ctx(%rip)
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movq %r9, 0x38 + cpu_ctx(%rip)
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movq %r10, 0x40 + cpu_ctx(%rip)
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movq %r11, 0x48 + cpu_ctx(%rip)
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movq %r12, 0x50 + cpu_ctx(%rip)
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movq %r13, 0x58 + cpu_ctx(%rip)
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movq %r14, 0x60 + cpu_ctx(%rip)
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movq %r15, 0x68 + cpu_ctx(%rip)
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pushfq
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popq CPU_CONTEXT_OFFSET_RFLAGS + cpu_ctx(%rip)
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/*168U=0xa8=CPU_CONTEXT_OFFSET_RFLAGS*/
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popq 0xa8 + cpu_ctx(%rip)
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sidt CPU_CONTEXT_OFFSET_IDTR + cpu_ctx(%rip)
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sldt CPU_CONTEXT_OFFSET_LDTR + cpu_ctx(%rip)
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/*504U=0x1f8=CPU_CONTEXT_OFFSET_IDTR*/
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sidt 0x1f8 + cpu_ctx(%rip)
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/*536U=0x218=CPU_CONTEXT_OFFSET_LDTR*/
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sldt 0x218 + cpu_ctx(%rip)
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mov %cr0, %rax
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mov %rax, CPU_CONTEXT_OFFSET_CR0 + cpu_ctx(%rip)
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/*120U=0x78=CPU_CONTEXT_OFFSET_CR0*/
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mov %rax, 0x78 + cpu_ctx(%rip)
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mov %cr3, %rax
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mov %rax, CPU_CONTEXT_OFFSET_CR3 + cpu_ctx(%rip)
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/*136U=0x88=CPU_CONTEXT_OFFSET_CR3*/
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mov %rax, 0x88 + cpu_ctx(%rip)
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mov %cr4, %rax
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mov %rax, CPU_CONTEXT_OFFSET_CR4 + cpu_ctx(%rip)
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/*144U=0x90=CPU_CONTEXT_OFFSET_CR4*/
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mov %rax, 0x90 + cpu_ctx(%rip)
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wbinvd
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movq CPU_CONTEXT_OFFSET_RDX + cpu_ctx(%rip), %rdx /* pm1b_cnt_val */
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movq CPU_CONTEXT_OFFSET_RDI + cpu_ctx(%rip), %rdi /* *vm */
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movq CPU_CONTEXT_OFFSET_RSI + cpu_ctx(%rip), %rsi /* pm1a_cnt_val */
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/*24U=0x18=CPU_CONTEXT_OFFSET_RDX*/
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movq 0x18 + cpu_ctx(%rip), %rdx /* pm1b_cnt_val */
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/*112U=0x70=CPU_CONTEXT_OFFSET_RDI*/
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movq 0x70 + cpu_ctx(%rip), %rdi /* *vm */
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/*40U=0x28=CPU_CONTEXT_OFFSET_RSI*/
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movq 0x28 + cpu_ctx(%rip), %rsi /* pm1a_cnt_val */
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call do_acpi_s3
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@ -70,41 +113,68 @@ __enter_s3:
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*/
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.global restore_s3_context
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restore_s3_context:
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mov CPU_CONTEXT_OFFSET_CR4 + cpu_ctx(%rip), %rax
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/*144U=0x90=CPU_CONTEXT_OFFSET_CR4*/
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mov 0x90 + cpu_ctx(%rip), %rax
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mov %rax, %cr4
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mov CPU_CONTEXT_OFFSET_CR3 + cpu_ctx(%rip), %rax
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/*136U=0x88=CPU_CONTEXT_OFFSET_CR3*/
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mov 0x88 + cpu_ctx(%rip), %rax
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mov %rax, %cr3
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mov CPU_CONTEXT_OFFSET_CR0 + cpu_ctx(%rip), %rax
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/*144U=0x90=CPU_CONTEXT_OFFSET_CR4*/
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mov 0x90 + cpu_ctx(%rip), %rax
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mov %rax, %cr0
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lidt CPU_CONTEXT_OFFSET_IDTR + cpu_ctx(%rip)
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lldt CPU_CONTEXT_OFFSET_LDTR + cpu_ctx(%rip)
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/*504U=0x1f8=CPU_CONTEXT_OFFSET_IDTR*/
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lidt 0x1f8 + cpu_ctx(%rip)
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/*536U=0x218=CPU_CONTEXT_OFFSET_LDTR*/
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lldt 0x218 + cpu_ctx(%rip)
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mov CPU_CONTEXT_OFFSET_SS + cpu_ctx(%rip), %ss
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mov CPU_CONTEXT_OFFSET_RSP + cpu_ctx(%rip), %rsp
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/*
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*312U=0x138=CPU_CONTEXT_OFFSET_SS
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*160=0xa0=CPU_CONTEXT_OFFSET_RSP
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*/
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mov 0x138 + cpu_ctx(%rip), %ss
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mov 0xa0 + cpu_ctx(%rip), %rsp
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pushq CPU_CONTEXT_OFFSET_RFLAGS + cpu_ctx(%rip)
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/*168U=0xa8=CPU_CONTEXT_OFFSET_RFLAGS*/
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pushq 0xa8 + cpu_ctx(%rip)
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popfq
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call load_gdtr_and_tr
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call restore_msrs
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movq CPU_CONTEXT_OFFSET_RAX + cpu_ctx(%rip), %rax
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movq CPU_CONTEXT_OFFSET_RBX + cpu_ctx(%rip), %rbx
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movq CPU_CONTEXT_OFFSET_RCX + cpu_ctx(%rip), %rcx
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movq CPU_CONTEXT_OFFSET_RDX + cpu_ctx(%rip), %rdx
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movq CPU_CONTEXT_OFFSET_RDI + cpu_ctx(%rip), %rdi
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movq CPU_CONTEXT_OFFSET_RSI + cpu_ctx(%rip), %rsi
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movq CPU_CONTEXT_OFFSET_RBP + cpu_ctx(%rip), %rbp
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movq CPU_CONTEXT_OFFSET_R8 + cpu_ctx(%rip), %r8
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movq CPU_CONTEXT_OFFSET_R9 + cpu_ctx(%rip), %r9
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movq CPU_CONTEXT_OFFSET_R10 + cpu_ctx(%rip), %r10
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movq CPU_CONTEXT_OFFSET_R11 + cpu_ctx(%rip), %r11
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movq CPU_CONTEXT_OFFSET_R12 + cpu_ctx(%rip), %r12
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movq CPU_CONTEXT_OFFSET_R13 + cpu_ctx(%rip), %r13
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movq CPU_CONTEXT_OFFSET_R14 + cpu_ctx(%rip), %r14
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movq CPU_CONTEXT_OFFSET_R15 + cpu_ctx(%rip), %r15
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/*
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* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
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* 8U=0x8=CPU_CONTEXT_OFFSET_RBX
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* 16U=0x10=CPU_CONTEXT_OFFSET_RCX
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* 24U=0x18=CPU_CONTEXT_OFFSET_RDX
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* 112U=0x70=CPU_CONTEXT_OFFSET_RDI
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* 40U=0x28=CPU_CONTEXT_OFFSET_RSI
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* 32U=0x20=CPU_CONTEXT_OFFSET_RBP
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* 48U=0x30=CPU_CONTEXT_OFFSET_R8
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* 56U=0x38=CPU_CONTEXT_OFFSET_R9
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* 64U=0x40=CPU_CONTEXT_OFFSET_R10
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* 72U=0x48=CPU_CONTEXT_OFFSET_R11
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* 80U=0x50=CPU_CONTEXT_OFFSET_R12
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* 88U=0x58=CPU_CONTEXT_OFFSET_R13
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* 96U=0x60=CPU_CONTEXT_OFFSET_R14
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* 104U=0x68=CPU_CONTEXT_OFFSET_R15
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*/
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movq 0x0 + cpu_ctx(%rip), %rax
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movq 0x8 + cpu_ctx(%rip), %rbx
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movq 0x10 + cpu_ctx(%rip), %rcx
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movq 0x18 + cpu_ctx(%rip), %rdx
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movq 0x70 + cpu_ctx(%rip), %rdi
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movq 0x28 + cpu_ctx(%rip), %rsi
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movq 0x20 + cpu_ctx(%rip), %rbp
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movq 0x30 + cpu_ctx(%rip), %r8
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||||
movq 0x38 + cpu_ctx(%rip), %r9
|
||||
movq 0x40 + cpu_ctx(%rip), %r10
|
||||
movq 0x48 + cpu_ctx(%rip), %r11
|
||||
movq 0x50 + cpu_ctx(%rip), %r12
|
||||
movq 0x58 + cpu_ctx(%rip), %r13
|
||||
movq 0x60 + cpu_ctx(%rip), %r14
|
||||
movq 0x68 + cpu_ctx(%rip), %r15
|
||||
|
||||
retq
|
||||
|
||||
@ -32,45 +32,45 @@
|
||||
#define CPU_CONTEXT_INDEX_R15 13
|
||||
#define CPU_CONTEXT_INDEX_RDI 14
|
||||
|
||||
#define CPU_CONTEXT_OFFSET_RAX 0
|
||||
#define CPU_CONTEXT_OFFSET_RBX 8
|
||||
#define CPU_CONTEXT_OFFSET_RCX 16
|
||||
#define CPU_CONTEXT_OFFSET_RDX 24
|
||||
#define CPU_CONTEXT_OFFSET_RBP 32
|
||||
#define CPU_CONTEXT_OFFSET_RSI 40
|
||||
#define CPU_CONTEXT_OFFSET_R8 48
|
||||
#define CPU_CONTEXT_OFFSET_R9 56
|
||||
#define CPU_CONTEXT_OFFSET_R10 64
|
||||
#define CPU_CONTEXT_OFFSET_R11 72
|
||||
#define CPU_CONTEXT_OFFSET_R12 80
|
||||
#define CPU_CONTEXT_OFFSET_R13 88
|
||||
#define CPU_CONTEXT_OFFSET_R14 96
|
||||
#define CPU_CONTEXT_OFFSET_R15 104
|
||||
#define CPU_CONTEXT_OFFSET_RDI 112
|
||||
#define CPU_CONTEXT_OFFSET_CR0 120
|
||||
#define CPU_CONTEXT_OFFSET_CR2 128
|
||||
#define CPU_CONTEXT_OFFSET_CR3 136
|
||||
#define CPU_CONTEXT_OFFSET_CR4 144
|
||||
#define CPU_CONTEXT_OFFSET_RAX 0U
|
||||
#define CPU_CONTEXT_OFFSET_RBX 8U
|
||||
#define CPU_CONTEXT_OFFSET_RCX 16U
|
||||
#define CPU_CONTEXT_OFFSET_RDX 24U
|
||||
#define CPU_CONTEXT_OFFSET_RBP 32U
|
||||
#define CPU_CONTEXT_OFFSET_RSI 40U
|
||||
#define CPU_CONTEXT_OFFSET_R8 48U
|
||||
#define CPU_CONTEXT_OFFSET_R9 56U
|
||||
#define CPU_CONTEXT_OFFSET_R10 64U
|
||||
#define CPU_CONTEXT_OFFSET_R11 72U
|
||||
#define CPU_CONTEXT_OFFSET_R12 80U
|
||||
#define CPU_CONTEXT_OFFSET_R13 88U
|
||||
#define CPU_CONTEXT_OFFSET_R14 96U
|
||||
#define CPU_CONTEXT_OFFSET_R15 104U
|
||||
#define CPU_CONTEXT_OFFSET_RDI 112U
|
||||
#define CPU_CONTEXT_OFFSET_CR0 120U
|
||||
#define CPU_CONTEXT_OFFSET_RIP 152
|
||||
#define CPU_CONTEXT_OFFSET_RSP 160
|
||||
#define CPU_CONTEXT_OFFSET_RFLAGS 168
|
||||
#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184
|
||||
#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192
|
||||
#define CPU_CONTEXT_OFFSET_IA32_STAR 200
|
||||
#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208
|
||||
#define CPU_CONTEXT_OFFSET_IA32_FMASK 216
|
||||
#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224
|
||||
#define CPU_CONTEXT_OFFSET_CS 280
|
||||
#define CPU_CONTEXT_OFFSET_SS 312
|
||||
#define CPU_CONTEXT_OFFSET_DS 344
|
||||
#define CPU_CONTEXT_OFFSET_ES 376
|
||||
#define CPU_CONTEXT_OFFSET_FS 408
|
||||
#define CPU_CONTEXT_OFFSET_GS 440
|
||||
#define CPU_CONTEXT_OFFSET_TR 472
|
||||
#define CPU_CONTEXT_OFFSET_IDTR 504
|
||||
#define CPU_CONTEXT_OFFSET_LDTR 536
|
||||
#define CPU_CONTEXT_OFFSET_GDTR 568
|
||||
#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608
|
||||
#define CPU_CONTEXT_OFFSET_CR2 128U
|
||||
#define CPU_CONTEXT_OFFSET_CR3 136U
|
||||
#define CPU_CONTEXT_OFFSET_CR4 144U
|
||||
#define CPU_CONTEXT_OFFSET_RSP 160U
|
||||
#define CPU_CONTEXT_OFFSET_RFLAGS 168U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192U
|
||||
#define CPU_CONTEXT_OFFSET_SS 312U
|
||||
#define CPU_CONTEXT_OFFSET_IDTR 504U
|
||||
#define CPU_CONTEXT_OFFSET_LDTR 536U
|
||||
|
||||
/*sizes of various registers within the VCPU data structure */
|
||||
#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user