From 8017ebdf823d8503e85b82aff0138518d3477a0a Mon Sep 17 00:00:00 2001 From: Huihuang Shi Date: Tue, 17 Jul 2018 10:41:27 +0800 Subject: [PATCH] HV:vtd:dma change the macro to the inline function Function like macro changed to be inline function to limit the return type and parameter type. V1->V2:change the apis to letter case. Signed-off-by: Huihuang Shi Acked-by: Eddie Dong --- hypervisor/arch/x86/vtd.c | 50 +++++----- hypervisor/include/arch/x86/vtd.h | 159 ++++++++++++++++++++++++------ 2 files changed, 156 insertions(+), 53 deletions(-) diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c index 6c9276185..d2f9146dd 100644 --- a/hypervisor/arch/x86/vtd.c +++ b/hypervisor/arch/x86/vtd.c @@ -565,11 +565,11 @@ static void dmar_invalid_context_cache(struct dmar_drhd_rt *dmar_uint, cmd |= DMA_CCMD_GLOBAL_INVL; break; case DMAR_CIRG_DOMAIN: - cmd |= DMA_CCMD_DOMAIN_INVL | DMA_CCMD_DID(did); + cmd |= DMA_CCMD_DOMAIN_INVL | dma_ccmd_did(did); break; case DMAR_CIRG_DEVICE: - cmd |= DMA_CCMD_DEVICE_INVL | DMA_CCMD_DID(did) | - DMA_CCMD_SID(sid) | DMA_CCMD_FM(fm); + cmd |= DMA_CCMD_DEVICE_INVL | dma_ccmd_did(did) | + dma_ccmd_sid(sid) | dma_ccmd_fm(fm); break; default: pr_err("unknown CIRG type"); @@ -585,7 +585,7 @@ static void dmar_invalid_context_cache(struct dmar_drhd_rt *dmar_uint, IOMMU_UNLOCK(dmar_uint); dev_dbg(ACRN_DBG_IOMMU, "cc invalidation granularity %d", - DMA_CCMD_GET_CAIG_32(status)); + dma_ccmd_get_caig_32(status)); } static void dmar_invalid_context_cache_global(struct dmar_drhd_rt *dmar_uint) @@ -609,11 +609,11 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint, cmd |= DMA_IOTLB_GLOBAL_INVL; break; case DMAR_IIRG_DOMAIN: - cmd |= DMA_IOTLB_DOMAIN_INVL | DMA_IOTLB_DID(did); + cmd |= DMA_IOTLB_DOMAIN_INVL | dma_iotlb_did(did); break; case DMAR_IIRG_PAGE: - cmd |= DMA_IOTLB_PAGE_INVL | DMA_IOTLB_DID(did); - addr = address | DMA_IOTLB_INVL_ADDR_AM(am); + cmd |= DMA_IOTLB_PAGE_INVL | dma_iotlb_did(did); + addr = address | dma_iotlb_invl_addr_am(am); if (hint) { addr |= DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED; } @@ -633,7 +633,7 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint, (status & DMA_IOTLB_IVT_32) == 0U, status); IOMMU_UNLOCK(dmar_uint); - if (DMA_IOTLB_GET_IAIG_32(status) == 0U) { + if (dma_iotlb_get_iaig_32(status) == 0U) { pr_err("fail to invalidate IOTLB!, 0x%x, 0x%x", status, iommu_read32(dmar_uint, DMAR_FSTS_REG)); } @@ -705,35 +705,35 @@ static void dmar_fault_msi_write(struct dmar_drhd_rt *dmar_uint, #if DBG_IOMMU static void fault_status_analysis(uint32_t status) { - if (DMA_FSTS_PFO(status)) { + if (dma_fsts_pfo(status)) { pr_info("Primary Fault Overflow"); } - if (DMA_FSTS_PPF(status)) { + if (dma_fsts_ppf(status)) { pr_info("Primary Pending Fault"); } - if (DMA_FSTS_AFO(status)) { + if (dma_fsts_afo(status)) { pr_info("Advanced Fault Overflow"); } - if (DMA_FSTS_APF(status)) { + if (dma_fsts_apf(status)) { pr_info("Advanced Pending Fault"); } - if (DMA_FSTS_IQE(status)) { + if (dma_fsts_iqe(status)) { pr_info("Invalidation Queue Error"); } - if (DMA_FSTS_ICE(status)) { + if (dma_fsts_ice(status)) { pr_info("Invalidation Completion Error"); } - if (DMA_FSTS_ITE(status)) { + if (dma_fsts_ite(status)) { pr_info("Invalidation Time-out Error"); } - if (DMA_FSTS_PRO(status)) { + if (dma_fsts_pro(status)) { pr_info("Page Request Overflow"); } } @@ -741,22 +741,22 @@ static void fault_status_analysis(uint32_t status) static void fault_record_analysis(__unused uint64_t low, uint64_t high) { - if (DMA_FRCD_UP_F(high) == 0U) { + if (dma_frcd_up_f(high)) { return; } /* currently skip PASID related parsing */ pr_info("%s, Reason: 0x%x, SID: %x.%x.%x @0x%llx", - (DMA_FRCD_UP_T(high) != 0U) ? "Read/Atomic" : "Write", - DMA_FRCD_UP_FR(high), - DMA_FRCD_UP_SID(high) >> 8, - (DMA_FRCD_UP_SID(high) >> 3) & 0x1fUL, - DMA_FRCD_UP_SID(high) & 0x7UL, + dma_frcd_up_t(high) ? "Read/Atomic" : "Write", + dma_frcd_up_fr(high), + dma_frcd_up_sid(high) >> 8, + (dma_frcd_up_sid(high) >> 3) & 0x1fUL, + dma_frcd_up_sid(high) & 0x7UL, low); #if DBG_IOMMU if (iommu_ecap_dt(dmar_uint->ecap)i != 0U) { pr_info("Address Type: 0x%x", - DMA_FRCD_UP_AT(high)); + dma_frcd_up_at(high)); } #endif } @@ -778,9 +778,9 @@ static int dmar_fault_handler(int irq, void *data) fault_status_analysis(fsr); #endif - while (DMA_FSTS_PPF(fsr) != 0U) { + while (dma_fsts_ppf(fsr)) { loop++; - index = DMA_FSTS_FRI(fsr); + index = dma_fsts_fri(fsr); record_reg_offset = dmar_uint->cap_fault_reg_offset + index * 16; if (index >= dmar_uint->cap_num_fault_regs) { diff --git a/hypervisor/include/arch/x86/vtd.h b/hypervisor/include/arch/x86/vtd.h index 1047192a1..2abd658a1 100644 --- a/hypervisor/include/arch/x86/vtd.h +++ b/hypervisor/include/arch/x86/vtd.h @@ -35,8 +35,15 @@ #define DMAR_ICS_REG 0x9cU /* Invalidation complete status register */ #define DMAR_IRTA_REG 0xb8U /* Interrupt remapping table addr register */ -#define DMAR_VER_MAJOR(v) (((v) & 0xf0U) >> 4) -#define DMAR_VER_MINOR(v) ((v) & 0x0fU) +static inline uint8_t dmar_ver_major(uint64_t version) +{ + return ((version & 0xf0UL) >> 4U); +} + +static inline uint8_t dmar_ver_minor(uint64_t version) +{ + return (version & 0x0fUL); +} /* * Decoding Capability Register @@ -282,14 +289,30 @@ static inline uint8_t iommu_ecap_pds(uint64_t ecap) #define DMA_CCMD_GLOBAL_INVL (((uint64_t)1UL) << 61) #define DMA_CCMD_DOMAIN_INVL (((uint64_t)2UL) << 61) #define DMA_CCMD_DEVICE_INVL (((uint64_t)3UL) << 61) -#define DMA_CCMD_FM(m) (((uint64_t)((m) & 0x3UL)) << 32) +static inline uint64_t dma_ccmd_fm(uint8_t fm) +{ + return (((uint64_t)(fm & 0x3U)) << 32U); +} + #define DMA_CCMD_MASK_NOBIT 0UL #define DMA_CCMD_MASK_1BIT 1UL #define DMA_CCMD_MASK_2BIT 2UL #define DMA_CCMD_MASK_3BIT 3UL -#define DMA_CCMD_SID(s) (((uint64_t)((s) & 0xffffUL)) << 16) -#define DMA_CCMD_DID(d) ((uint64_t)((d) & 0xffffUL)) -#define DMA_CCMD_GET_CAIG_32(v) (((uint32_t)(v) >> 27) & 0x3U) +static inline uint64_t dma_ccmd_sid(uint16_t sid) +{ + return (((uint64_t)(sid & 0xffffU)) << 16U); +} + +static inline uint16_t dma_ccmd_did(uint16_t did) +{ + return (did & 0xffffU); +} + +static inline uint8_t dma_ccmd_get_caig_32(uint32_t gaig) +{ + return ((gaig >> 27U) & 0x3U); +} + /* IOTLB_REG */ #define DMA_IOTLB_IVT (((uint64_t)1UL) << 63) @@ -299,38 +322,118 @@ static inline uint8_t iommu_ecap_pds(uint64_t ecap) #define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60) #define DMA_IOTLB_DR (((uint64_t)1UL) << 49) #define DMA_IOTLB_DW (((uint64_t)1UL) << 48) -#define DMA_IOTLB_DID(d) \ - (((uint64_t)((d) & 0xffffUL)) << 32) -#define DMA_IOTLB_GET_IAIG_32(v) (((uint32_t)(v) >> 25) & 0x3U) +static inline uint64_t dma_iotlb_did(uint16_t did) +{ + return (((uint64_t)(did & 0xffffU)) << 32U); +} + +static inline uint8_t dma_iotlb_get_iaig_32(uint32_t iai) +{ + return ((iai >> 25U) & 0x3U); +} /* INVALIDATE_ADDRESS_REG */ -#define DMA_IOTLB_INVL_ADDR_AM(m) ((uint64_t)((m) & 0x3fUL)) +static inline uint8_t dma_iotlb_invl_addr_am(uint8_t am) +{ + return (am & 0x3fU); +} + #define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6) /* FECTL_REG */ #define DMA_FECTL_IM (((uint32_t)1U) << 31) /* FSTS_REG */ -#define DMA_FSTS_PFO(s) (((s) >> 0) & 1U) -#define DMA_FSTS_PPF(s) (((s) >> 1) & 1U) -#define DMA_FSTS_AFO(s) (((s) >> 2) & 1U) -#define DMA_FSTS_APF(s) (((s) >> 3) & 1U) -#define DMA_FSTS_IQE(s) (((s) >> 4) & 1U) -#define DMA_FSTS_ICE(s) (((s) >> 5) & 1U) -#define DMA_FSTS_ITE(s) (((s) >> 6) & 1U) -#define DMA_FSTS_PRO(s) (((s) >> 7) & 1U) -#define DMA_FSTS_FRI(s) (((s) >> 8) & 0xFFU) +static inline bool dma_fsts_pfo(uint32_t PFO) +{ + return ((PFO >> 0U) & 1U) == 1U; +} + +static inline bool dma_fsts_ppf(uint32_t PPF) +{ + return ((PPF >> 1U) & 1U) == 1U; +} + +static inline bool dma_fsts_afo(uint32_t AFO) +{ + return ((AFO >> 2U) & 1U) == 1U; +} + +static inline bool dma_fsts_apf(uint32_t APF) +{ + return ((APF >> 3U) & 1U) == 1U; +} + +static inline bool dma_fsts_iqe(uint32_t IQE) +{ + return ((IQE >> 4U) & 1U) == 1U; +} + +static inline bool dma_fsts_ice(uint32_t ICE) +{ + return ((ICE >> 5U) & 1U) == 1U; +} + +static inline bool dma_fsts_ite(uint32_t ITE) +{ + return ((ITE >> 6U) & 1U) == 1U; +} + +static inline bool dma_fsts_pro(uint32_t PRO) +{ + return ((PRO >> 7U) & 1U) == 1U; +} + +static inline uint8_t dma_fsts_fri(uint32_t FRI) +{ + return ((FRI >> 8U) & 0xFFU); +} /* FRCD_REGs: upper 64 bits*/ -#define DMA_FRCD_UP_F(r) (((r) >> 63) & 1UL) -#define DMA_FRCD_UP_T(r) (((r) >> 62) & 1UL) -#define DMA_FRCD_UP_AT(r) (((r) >> 60) & 3UL) -#define DMA_FRCD_UP_PASID(r) (((r) >> 40) & 0xfffffUL) -#define DMA_FRCD_UP_FR(r) (((r) >> 32) & 0xffUL) -#define DMA_FRCD_UP_PP(r) (((r) >> 31) & 1UL) -#define DMA_FRCD_UP_EXE(r) (((r) >> 30) & 1UL) -#define DMA_FRCD_UP_PRIV(r) (((r) >> 29) & 1UL) -#define DMA_FRCD_UP_SID(r) (((r) >> 0) & 0xffffUL) +static inline bool dma_frcd_up_f(uint64_t UP_F) +{ + return ((UP_F >> 63U) & 1UL) == 1UL; +} + +static inline uint8_t dma_frcd_up_t(uint64_t UP_T) +{ + return ((UP_T >> 62U) & 1UL); +} + +static inline uint8_t dma_frcd_up_at(uint64_t UP_AT) +{ + return ((UP_AT >> 60U) & 3UL); +} + +static inline uint32_t dma_frcd_up_pasid(uint64_t UP_PASID) +{ + return ((UP_PASID >> 40U) & 0xfffffUL); +} + +static inline uint8_t dma_frcd_up_fr(uint64_t UP_FR) +{ + return ((UP_FR >> 32U) & 0xffUL); +} + +static inline bool dma_frcd_up_pp(uint64_t UP_PP) +{ + return ((UP_PP >> 31U) & 1UL) == 1UL; +} + +static inline bool dma_frcd_up_exe(uint64_t UP_EXE) +{ + return ((UP_EXE >> 30U) & 1UL) == 1UL; +} + +static inline bool dma_frcd_up_priv(uint64_t UP_PRIV) +{ + return ((UP_PRIV >> 29U) & 1UL) == 1UL; +} + +static inline uint32_t dma_frcd_up_sid(uint64_t UP_SID) +{ + return ((UP_SID >> 0U) & 0xffffUL); +} #define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U #define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U