From 80a7281f1ef02a6b403fb427ce74b80a86f34044 Mon Sep 17 00:00:00 2001 From: Wei Liu Date: Mon, 2 Dec 2019 10:04:37 +0800 Subject: [PATCH] acrn-config: add MMCFG_BASE_INFO item in board config Parse MMCFG base address value and store it to board config xml as DEFAULT_PCI_MMCFG_BASE macro. Tracked-On: #4173 Signed-off-by: Wei Liu Acked-by: Victor Sun --- misc/acrn-config/xmls/board-xmls/apl-mrb.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/apl-up2.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/nuc6cayh.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml | 5 +++++ misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml | 5 +++++ 7 files changed, 35 insertions(+) diff --git a/misc/acrn-config/xmls/board-xmls/apl-mrb.xml b/misc/acrn-config/xmls/board-xmls/apl-mrb.xml index 41f55df3c..336928fa4 100644 --- a/misc/acrn-config/xmls/board-xmls/apl-mrb.xml +++ b/misc/acrn-config/xmls/board-xmls/apl-mrb.xml @@ -253,6 +253,11 @@ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P16 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:L2 clos max:4 diff --git a/misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml b/misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml index 924cc6ae9..84bd32d1a 100644 --- a/misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml +++ b/misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml @@ -227,6 +227,11 @@ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:L2 clos max:4 diff --git a/misc/acrn-config/xmls/board-xmls/apl-up2.xml b/misc/acrn-config/xmls/board-xmls/apl-up2.xml index 964b355ba..b955863fe 100644 --- a/misc/acrn-config/xmls/board-xmls/apl-up2.xml +++ b/misc/acrn-config/xmls/board-xmls/apl-up2.xml @@ -227,6 +227,11 @@ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:L2 clos max:4 diff --git a/misc/acrn-config/xmls/board-xmls/nuc6cayh.xml b/misc/acrn-config/xmls/board-xmls/nuc6cayh.xml index 978f58842..baec30218 100644 --- a/misc/acrn-config/xmls/board-xmls/nuc6cayh.xml +++ b/misc/acrn-config/xmls/board-xmls/nuc6cayh.xml @@ -183,6 +183,11 @@ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P8 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:L2 clos max:4 diff --git a/misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml b/misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml index f2694c577..f8713b8a5 100644 --- a/misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml +++ b/misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml @@ -181,6 +181,11 @@ {0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P15 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:False clos max:0 diff --git a/misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml b/misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml index 5e8b1f652..2bafdb59e 100644 --- a/misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml +++ b/misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml @@ -173,6 +173,11 @@ {0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P5 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:False clos max:0 diff --git a/misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml b/misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml index f8c47dc29..4fdaa296e 100644 --- a/misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml +++ b/misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml @@ -177,6 +177,11 @@ {0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */ + + /* PCI mmcfg base of MCFG */ + #define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + + clos supported by cache:False clos max:0