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hv: Add APIs to convert x2APIC MSR accesses to LAPIC MMIO offset

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This patch converts x2APIC MSR accesses to corresponding LAPIC MMIO offset to
utitlize vlapic_write/read APIs to virtualize LAPIC. Also adds support to inject
GP fault when read-only registers are attempted to be written to or vice versa.

Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This commit is contained in:
Sainath Grandhi
2018-11-01 15:04:29 -07:00
committed by lijinxia
parent e9fe6efd81
commit 80b6e62735
2 changed files with 51 additions and 10 deletions
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25
hypervisor/include/arch/x86/msr.h
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@@ -541,6 +541,31 @@ static inline bool is_x2apic_msr(uint32_t msr)
}
return ret;
}
static inline bool is_x2apic_read_only_msr(uint32_t msr)
{
bool ret = false;
if ((msr == MSR_IA32_EXT_XAPICID) ||
(msr == MSR_IA32_EXT_APIC_VERSION) ||
(msr == MSR_IA32_EXT_APIC_PPR) ||
(msr == MSR_IA32_EXT_APIC_LDR) ||
((msr >= MSR_IA32_EXT_APIC_ISR0) &&
(msr <= MSR_IA32_EXT_APIC_IRR7)) ||
(msr == MSR_IA32_EXT_APIC_CUR_COUNT)) {
ret = true;
}
return ret;
}
static inline bool is_x2apic_write_only_msr(uint32_t msr)
{
bool ret = false;
if ((msr == MSR_IA32_EXT_APIC_EOI) || (msr == MSR_IA32_EXT_APIC_SELF_IPI)) {
ret = true;
}
return ret;
}
#endif /* ASSEMBLER */
/* 5 high-order bits in every field are reserved */