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hv: vmx_capability: add cpu_has_vmx_ept/vpid_cap API

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Refine and simple vmx_capability API defination.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li, Fei1
2018-04-13 13:14:12 +08:00
committed by Jack Ren
parent d7d2ef8c88
commit 80d194cfb5
3 changed files with 54 additions and 63 deletions
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10
hypervisor/include/arch/x86/msr.h
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@@ -515,16 +515,6 @@
/* LINCROFT specific MSRs */
#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0 /* Configure CAR */
/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
#define MSR_VMX_EPT_X_ONLY (1UL << 0)/* Execute Only */
#define MSR_VMX_EPT_VPID_CAP_1GB (1UL << 17)/* EPT 1GB page */
#define MSR_VMX_INVEPT (1UL << 20)/* INVEPT */
#define MSR_VMX_INVEPT_SINGLE_CONTEXT (1UL << 25)/* INVEPT Single */
#define MSR_VMX_INVEPT_GLOBAL_CONTEXT (1UL << 26)/* INVEPT Global */
#define MSR_VMX_INVVPID (1UL << 32)/* INVVPID */
#define MSR_VMX_INVVPID_SINGLE_CONTEXT (1UL << 41)/* INVVPID Single */
#define MSR_VMX_INVVPID_GLOBAL_CONTEXT (1UL << 42)/* INVVPID Global */
/* EFER bits */
#define MSR_IA32_EFER_SCE_BIT (1<<0)
#define MSR_IA32_EFER_LME_BIT (1<<8) /* IA32e mode enable */

28
hypervisor/include/arch/x86/vmx.h
View File

@@ -325,6 +325,34 @@
#define VMX_PROCBASED_CTLS2_EPT_VE (1<<18)
#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1<<20)
/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
#define VMX_EPT_EXECUTE_ONLY (1 << 0)
#define VMX_EPT_PAGE_WALK_4 (1 << 6)
#define VMX_EPT_PAGE_WALK_5 (1 << 7)
#define VMX_EPTP_UC (1 << 8)
#define VMX_EPTP_WB (1 << 14)
#define VMX_EPT_2MB_PAGE (1 << 16)
#define VMX_EPT_1GB_PAGE (1 << 17)
#define VMX_EPT_INVEPT (1 << 20)
#define VMX_EPT_AD (1 << 21)
#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1 << 25)
#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1 << 26)
#define VMX_VPID_INVVPID (1 << 0) /* (32 - 32) */
#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1 << 8) /* (40 - 32) */
#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1 << 9) /* (41 - 32) */
#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1 << 10) /* (42 - 32) */
#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1 << 11) /* (43 - 32) */
#define VMX_EPT_MT_EPTE_SHIFT 3
#define VMX_EPTP_PWL_MASK 0x38
#define VMX_EPTP_PWL_4 0x18
#define VMX_EPTP_PWL_5 0x20
#define VMX_EPTP_AD_ENABLE_BIT (1 << 6)
#define VMX_EPTP_MT_MASK 0x7
#define VMX_EPTP_MT_WB 0x6
#define VMX_EPTP_MT_UC 0x0
/* VMX exit control bits */
#define VMX_EXIT_CTLS_SAVE_DBG (1<<2)
#define VMX_EXIT_CTLS_HOST_ADDR64 (1<<9)