github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-24 14:33:38 +00:00
Code Issues Projects Releases Wiki Activity

hv: fix possible SSE region mismatch issue

Browse Source 
During context switch in hypervisor, xsave/xrstore are used to
save/resotre the XSAVE area according to the XCR0 and XSS. The legacy
region in XSAVE area include FPU and SSE, we should make sure the
legacy region be saved during contex switch. FPU in XCR0 is always
enabled according to SDM.
For SSE, we enable it in XCR0 during context switch.

Tracked-On: #5062
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Conghui Chen 2020-07-15 00:09:17 +00:00 committed by wenlingz
parent 53d4a7169b
commit 821c65b40c
3 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hypervisor/arch/x86/cpu_caps.c
View File

@ -481,6 +481,9 @@ int32_t detect_hardware_support(void)
} else if (!pcpu_has_cap(X86_FEATURE_XSAVES)) {
printf("%s, XSAVES not supported\n", __func__);
ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_SSE)) {
printf("%s, SSE not supported\n", __func__);
ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_COMPACTION_EXT)) {
printf("%s, Compaction extensions in XSAVE is not supported\n", __func__);
ret = -ENODEV;

4
hypervisor/arch/x86/guest/vcpu.c
View File

@ -754,14 +754,16 @@ void save_xsave_area(struct ext_context *ectx)
{
ectx->xcr0 = read_xcr(0);
ectx->xss = msr_read(MSR_IA32_XSS);
write_xcr(0, ectx->xcr0 | XSAVE_SSE);
xsaves(&ectx->xs_area, UINT64_MAX);
}
void rstore_xsave_area(const struct ext_context *ectx)
{
write_xcr(0, ectx->xcr0);
write_xcr(0, ectx->xcr0 | XSAVE_SSE);
msr_write(MSR_IA32_XSS, ectx->xss);
xrstors(&ectx->xs_area, UINT64_MAX);
write_xcr(0, ectx->xcr0);
}
/* TODO:

1
hypervisor/include/arch/x86/cpu.h
View File

@ -158,6 +158,7 @@
#define XSAVE_COMPACTED_FORMAT (1UL << 63U)
#define XSAVE_FPU (1UL << 0U)
#define XSAVE_SSE (1UL << 1U)
#define CPU_CONTEXT_OFFSET_RAX 0U
#define CPU_CONTEXT_OFFSET_RCX 8U