From 8254b2be65f4419d182de527bd0e6676f2daa9ef Mon Sep 17 00:00:00 2001
From: li shuang <shuangx.li@intel.com>
Date: Tue, 2 Feb 2021 13:42:16 +0800
Subject: [PATCH] config_tools: add PTCT configs

add PTCT table template on ehl-crb-b, update PTCT table template
on tgl-rvp, add SofwareSRAM in ehl-crb-b.xml

Tracked-On: #5649

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
---
 .../config_tools/acpi_template/ehl-crb-b/PTCT | Bin 0 -> 340 bytes
 misc/config_tools/acpi_template/tgl-rvp/PTCT  | Bin 324 -> 388 bytes
 .../config_tools/data/ehl-crb-b/ehl-crb-b.xml |  19 ++++++++++++++++++
 3 files changed, 19 insertions(+)
 create mode 100644 misc/config_tools/acpi_template/ehl-crb-b/PTCT

diff --git a/misc/config_tools/acpi_template/ehl-crb-b/PTCT b/misc/config_tools/acpi_template/ehl-crb-b/PTCT
new file mode 100644
index 0000000000000000000000000000000000000000..49cf5b04f920be273289107f554b1225a878d903
GIT binary patch
literal 340
zcma)$F$%&!5JmrL)CdX|7M3X_SSX0CO+ZtKK`izFUMTnQ7#_|4mPG7y!k^uld6~cW
zc#1Jd;c>aex+&`O^-wrQlH6(L9&Hu;Nee6M<RkT_KI!LHIgnQF!oYuP?TVd7h$`h7
zIZOQ5x1JfMVaL2E@(;839z5BzW8}bxn*Z>|hkX;P=b5z@@edEQ0sO%)4dU%LR^;bV
FdIJIR3;_TD

literal 0
HcmV?d00001

diff --git a/misc/config_tools/acpi_template/tgl-rvp/PTCT b/misc/config_tools/acpi_template/tgl-rvp/PTCT
index cd2ee449ab1a650adf1296055308b3cdc7c5e633..6fa6fbad91e2f940655fb26bef2c56238b3ae15e 100644
GIT binary patch
delta 85
zcmX@Y)WXaa5aJxt!pOkDSU-_#nzaH0BLgb~0|OHfGca&CfGGxkAjJZN3=F99Jjn7B
LXD?&6XJ7yTvF8XT

delta 25
hcmZo+KElKm5aJx-!pOkDcz+_-w22QEG8;26003M{2QdHu

diff --git a/misc/config_tools/data/ehl-crb-b/ehl-crb-b.xml b/misc/config_tools/data/ehl-crb-b/ehl-crb-b.xml
index 09ffe4775..65dc1c18e 100644
--- a/misc/config_tools/data/ehl-crb-b/ehl-crb-b.xml
+++ b/misc/config_tools/data/ehl-crb-b/ehl-crb-b.xml
@@ -422,4 +422,23 @@
 	16
 	</MAX_MSIX_TABLE_NUM>
 
+	<RTCT>
+		<SoftwareSRAM>
+			<cache_level>2</cache_level>
+			<base>0x40000000</base>
+			<ways>0xc00</ways>
+			<size>0x40000</size>
+			<apic_id>0x4</apic_id>
+			<apic_id>0x6</apic_id>
+		</SoftwareSRAM>
+		<SoftwareSRAM>
+			<cache_level>3</cache_level>
+			<base>0x40000000</base>
+			<ways>0xc000</ways>
+			<size>0x80000</size>
+			<apic_id>0x4</apic_id>
+			<apic_id>0x6</apic_id>
+		</SoftwareSRAM>
+	</RTCT>
+
 </acrn-config>