From 8553a1d35dec06b6a12e95a5b2ec4ecb296e7e68 Mon Sep 17 00:00:00 2001
From: Liang Yi <yi.liang@intel.com>
Date: Mon, 9 Aug 2021 14:39:47 +0800
Subject: [PATCH] hv: use per platform maximum physical address width

MAXIMUM_PA_WIDTH will be calculated from board information.

Tracked-On: #6357
Signed-off-by: Liang Yi <yi.liang@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
---
 hypervisor/include/arch/x86/asm/page.h    | 2 +-
 misc/config_tools/xforms/board_info.h.xsl | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hypervisor/include/arch/x86/asm/page.h b/hypervisor/include/arch/x86/asm/page.h
index 2d78634cb..c8e82b741 100644
--- a/hypervisor/include/arch/x86/asm/page.h
+++ b/hypervisor/include/arch/x86/asm/page.h
@@ -8,12 +8,12 @@
 #define PAGE_H
 
 #include <asm/lib/spinlock.h>
+#include <board_info.h>
 
 #define PAGE_SHIFT	12U
 #define PAGE_SIZE	(1U << PAGE_SHIFT)
 #define PAGE_MASK	0xFFFFFFFFFFFFF000UL
 
-#define MAXIMUM_PA_WIDTH	46U	/* maximum physical-address width */
 #define MAX_PHY_ADDRESS_SPACE	(1UL << MAXIMUM_PA_WIDTH)
 
 /* size of the low MMIO address space: 2GB */
diff --git a/misc/config_tools/xforms/board_info.h.xsl b/misc/config_tools/xforms/board_info.h.xsl
index 8179604e5..87da38ce4 100644
--- a/misc/config_tools/xforms/board_info.h.xsl
+++ b/misc/config_tools/xforms/board_info.h.xsl
@@ -37,6 +37,10 @@
   <xsl:template match="board-data/acrn-config">
     <xsl:call-template name="MAX_PCPU_NUM" />
     <xsl:call-template name="MAX_VMSIX_ON_MSI_PDEVS_NUM" />
+    <xsl:variable name="physical_address_bits" select="//processors/model/attribute[@id='physical_address_bits']/text()" />
+    <xsl:if test="$physical_address_bits">
+      <xsl:value-of select="acrn:define('MAXIMUM_PA_WIDTH', $physical_address_bits[1], 'U')" />
+    </xsl:if>
   </xsl:template>
 
   <xsl:template match="allocation-data/acrn-config">