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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 05:02:24 +00:00
dm: add thread for usb doorbell array write
Host doorbell array write can be asynchronous, so add an async thread which is used to deal doorbell write. Tracked-On: #8504 Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@intel.com> Reviewed-by: Jian Jun Chen <jian.jun.chen@intel.com>
This commit is contained in:
Yuanyuan Zhao
acrnsi-robot
parent
64d999e703
commit
863f220a19
@ -384,6 +384,12 @@ struct pci_xhci_vbdp_dev_state {
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uint8_t state;
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};
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struct pci_xhci_async_request_node {
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STAILQ_ENTRY(pci_xhci_async_request_node) link;
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uint64_t offset;
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uint64_t value;
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};
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struct pci_xhci_vdev {
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struct pci_vdev *dev;
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pthread_mutex_t mtx;
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@ -424,6 +430,12 @@ struct pci_xhci_vdev {
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int vbdp_dev_num;
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struct pci_xhci_vbdp_dev_state vbdp_devs[XHCI_MAX_VIRT_PORTS];
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pthread_t async_thread;
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bool async_transfer;
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pthread_cond_t async_cond;
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pthread_mutex_t async_tmx;
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STAILQ_HEAD(, pci_xhci_async_request_node) async_head;
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/*
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* native_ports uses for record the command line assigned native root
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* hub ports and its child external hub ports.
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@ -485,6 +497,7 @@ static int pci_xhci_parse_extcap(struct pci_xhci_vdev *xdev, char *opts);
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static int pci_xhci_convert_speed(int lspeed);
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static void pci_xhci_free_usb_xfer(struct pci_xhci_dev_emu *dev, struct usb_xfer *xfer);
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static void pci_xhci_isoc_handler(void *arg, uint64_t param);
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static void pci_xhci_async_enqueue(struct pci_xhci_vdev *xdev, uint64_t offset, uint64_t value);
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#define XHCI_OPT_MAX_LEN 32
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static struct pci_xhci_option_elem xhci_option_table[] = {
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@ -1982,7 +1995,9 @@ pci_xhci_cmd_disable_slot(struct pci_xhci_vdev *xdev, uint32_t slot)
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slot, di->path.bus, usb_dev_path(&di->path));
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/* release all the resource allocated for virtual device */
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pthread_mutex_unlock(&xdev->mtx);
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pci_xhci_dev_destroy(dev);
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pthread_mutex_lock(&xdev->mtx);
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} else
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UPRINTF(LWRN, "invalid slot %d\r\n", slot);
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@ -2056,6 +2071,7 @@ pci_xhci_cmd_address_device(struct pci_xhci_vdev *xdev,
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struct usb_native_devinfo *di;
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uint32_t cmderr;
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uint8_t rh_port;
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int ret;
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input_ctx = XHCI_GADDR(xdev, trb->qwTrb0 & ~0xFUL);
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if (!input_ctx) {
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@ -2110,7 +2126,10 @@ pci_xhci_cmd_address_device(struct pci_xhci_vdev *xdev,
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"port %d\r\n", di->path.bus,
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usb_dev_path(&di->path), rh_port);
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pthread_mutex_unlock(&xdev->mtx);
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dev = pci_xhci_dev_create(xdev, di);
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pthread_mutex_lock(&xdev->mtx);
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if (!dev) {
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UPRINTF(LFTL, "fail to create device for %d-%s\r\n",
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di->path.bus,
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@ -2142,8 +2161,15 @@ pci_xhci_cmd_address_device(struct pci_xhci_vdev *xdev,
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dev->hci.hci_address = slot;
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dev->dev_ctx = dev_ctx;
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if (dev->dev_ue->ue_reset == NULL ||
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dev->dev_ue->ue_reset(dev->dev_instance) < 0) {
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if (dev->dev_ue->ue_reset == NULL) {
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cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
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goto done;
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}
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pthread_mutex_unlock(&xdev->mtx);
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ret = dev->dev_ue->ue_reset(dev->dev_instance);
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pthread_mutex_lock(&xdev->mtx);
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if (ret < 0) {
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cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
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goto done;
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}
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@ -2391,6 +2417,7 @@ pci_xhci_cmd_reset_ep(struct pci_xhci_vdev *xdev,
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devep = &dev->eps[epid];
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pthread_mutex_lock(&devep->mtx);
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pthread_mutex_unlock(&xdev->mtx);
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xfer = devep->ep_xfer;
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for (i = 0; i < xfer->max_blk_cnt; ++i) {
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@ -2413,6 +2440,7 @@ pci_xhci_cmd_reset_ep(struct pci_xhci_vdev *xdev,
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UPRINTF(LDBG, "reset ep[%u] %08x %08x %016lx %08x\r\n",
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epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
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ep_ctx->dwEpCtx4);
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pthread_mutex_lock(&xdev->mtx);
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pthread_mutex_unlock(&devep->mtx);
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done:
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@ -3022,8 +3050,10 @@ pci_xhci_try_usb_xfer(struct pci_xhci_vdev *xdev,
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/* outstanding requests queued up */
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if (dev->dev_ue->ue_data != NULL) {
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pthread_mutex_unlock(&xdev->mtx);
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err = dev->dev_ue->ue_data(dev->dev_instance, xfer, epid & 0x1 ?
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USB_XFER_IN : USB_XFER_OUT, epid/2);
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pthread_mutex_lock(&xdev->mtx);
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if (err == USB_ERR_CANCELLED) {
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if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) ==
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USB_NAK)
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@ -3286,8 +3316,11 @@ retry:
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if (epid == 1) {
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err = USB_ERR_NOT_STARTED;
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if (dev->dev_ue->ue_request != NULL)
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if (dev->dev_ue->ue_request != NULL) {
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pthread_mutex_unlock(&xdev->mtx);
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err = dev->dev_ue->ue_request(dev->dev_instance, xfer);
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pthread_mutex_lock(&xdev->mtx);
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}
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setup_trb = NULL;
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} else {
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/* handle data transfer */
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@ -3658,21 +3691,24 @@ pci_xhci_write(struct vmctx *ctx,
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xdev = dev->arg;
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pthread_mutex_lock(&xdev->mtx);
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if (offset < XHCI_CAPLEN) /* read only registers */
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UPRINTF(LWRN, "write RO-CAPs offset %ld\r\n", offset);
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else if (offset < xdev->dboff)
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else if (offset < xdev->dboff) {
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pthread_mutex_lock(&xdev->mtx);
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pci_xhci_hostop_write(xdev, offset, value);
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else if (offset < xdev->rtsoff)
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pci_xhci_dbregs_write(xdev, offset, value);
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else if (offset < xdev->rtsend)
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pthread_mutex_unlock(&xdev->mtx);
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} else if (offset < xdev->rtsoff) {
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pci_xhci_async_enqueue(xdev, offset, value);
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} else if (offset < xdev->rtsend) {
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pthread_mutex_lock(&xdev->mtx);
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pci_xhci_rtsregs_write(xdev, offset, value);
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else if (offset < xdev->regsend)
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pthread_mutex_unlock(&xdev->mtx);
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} else if (offset < xdev->regsend) {
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pthread_mutex_lock(&xdev->mtx);
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pci_xhci_excap_write(xdev, offset, value);
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else
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pthread_mutex_unlock(&xdev->mtx);
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} else
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UPRINTF(LWRN, "write invalid offset %ld\r\n", offset);
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pthread_mutex_unlock(&xdev->mtx);
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}
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static uint64_t
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@ -3901,25 +3937,29 @@ pci_xhci_read(struct vmctx *ctx,
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uint32_t value;
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xdev = dev->arg;
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pthread_mutex_lock(&xdev->mtx);
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if (offset < XHCI_CAPLEN)
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if (offset < XHCI_CAPLEN) {
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pthread_mutex_lock(&xdev->mtx);
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value = pci_xhci_hostcap_read(xdev, offset);
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else if (offset < xdev->dboff)
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pthread_mutex_unlock(&xdev->mtx);
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} else if (offset < xdev->dboff) {
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pthread_mutex_lock(&xdev->mtx);
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value = pci_xhci_hostop_read(xdev, offset);
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else if (offset < xdev->rtsoff)
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pthread_mutex_unlock(&xdev->mtx);
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} else if (offset < xdev->rtsoff) {
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value = pci_xhci_dbregs_read(xdev, offset);
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else if (offset < xdev->rtsend)
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} else if (offset < xdev->rtsend) {
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pthread_mutex_lock(&xdev->mtx);
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value = pci_xhci_rtsregs_read(xdev, offset);
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else if (offset < xdev->regsend)
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pthread_mutex_unlock(&xdev->mtx);
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} else if (offset < xdev->regsend) {
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pthread_mutex_lock(&xdev->mtx);
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value = pci_xhci_excap_read(xdev, offset);
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else {
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pthread_mutex_unlock(&xdev->mtx);
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} else {
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value = 0;
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UPRINTF(LDBG, "read invalid offset %ld\r\n", offset);
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}
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pthread_mutex_unlock(&xdev->mtx);
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switch (size) {
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case 1:
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value &= 0xFF;
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@ -4005,6 +4045,7 @@ pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
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struct xhci_endp_ctx *ep_ctx;
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int dir_in;
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int epid;
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int ret = 0;
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dir_in = epctx & 0x80;
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epid = epctx & ~0x80;
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@ -4018,10 +4059,11 @@ pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
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xdev = dev->xdev;
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/* check if device is ready; OS has to initialise it */
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pthread_mutex_lock(&xdev->mtx);
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if (xdev->rtsregs.erstba_p == NULL ||
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(xdev->opregs.usbcmd & XHCI_CMD_RS) == 0 ||
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dev->dev_ctx == NULL)
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return 0;
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goto out;
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p = XHCI_PORTREG_PTR(xdev, hci->hci_port);
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@ -4030,16 +4072,18 @@ pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
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p->portsc &= ~XHCI_PS_PLS_MASK;
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p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME);
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if ((p->portsc & XHCI_PS_PLC) != 0)
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return 0;
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goto out;
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p->portsc |= XHCI_PS_PLC;
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pci_xhci_set_evtrb(&evtrb, hci->hci_port,
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XHCI_TRB_ERROR_SUCCESS,
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XHCI_TRB_EVENT_PORT_STS_CHANGE);
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if (pci_xhci_insert_event(xdev, &evtrb, 0) != 0) {
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UPRINTF(LFTL, "Failed to inject port status change event!\r\n");
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return -ENAVAIL;
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ret = -ENAVAIL;
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goto out;
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}
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}
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@ -4048,14 +4092,15 @@ pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
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if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) {
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UPRINTF(LWRN, "device interrupt on disabled endpoint %d\r\n",
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epid);
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return 0;
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goto out;
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}
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UPRINTF(LDBG, "device interrupt on endpoint %d\r\n", epid);
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pci_xhci_device_doorbell(xdev, hci->hci_port, epid, 0);
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return 0;
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out:
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pthread_mutex_unlock(&xdev->mtx);
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return ret;
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}
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static int
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@ -4418,6 +4463,55 @@ pci_xhci_isoc_handler(void *arg, uint64_t param)
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? "under" : "over", pdata->slot, pdata->epnum);
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}
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static void
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pci_xhci_async_enqueue(struct pci_xhci_vdev *xdev, uint64_t offset, uint64_t value)
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{
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struct pci_xhci_async_request_node *request;
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request = malloc(sizeof(struct pci_xhci_async_request_node));
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if (request == NULL) {
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UPRINTF(LFTL, "%s: malloc memory fail\r\n", __func__);
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return;
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}
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request->offset = offset;
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request->value = value;
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pthread_mutex_lock(&xdev->async_tmx);
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if (STAILQ_EMPTY(&xdev->async_head)) {
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STAILQ_INSERT_HEAD(&xdev->async_head, request, link);
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} else {
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STAILQ_INSERT_TAIL(&xdev->async_head, request, link);
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}
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pthread_cond_signal(&xdev->async_cond);
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pthread_mutex_unlock(&xdev->async_tmx);
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}
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static void *
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pci_xhci_ansyc_thread(void *data)
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{
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struct pci_xhci_vdev *xdev;
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struct pci_xhci_async_request_node *request;
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xdev = data;
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pthread_mutex_lock(&xdev->async_tmx);
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while (xdev->async_transfer || !STAILQ_EMPTY(&xdev->async_head)) {
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if(STAILQ_EMPTY(&xdev->async_head))
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pthread_cond_wait(&xdev->async_cond, &xdev->async_tmx);
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if ((request = STAILQ_FIRST(&xdev->async_head)) == NULL) {
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continue;
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}
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pthread_mutex_unlock(&xdev->async_tmx);
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pthread_mutex_lock(&xdev->mtx);
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pci_xhci_dbregs_write(xdev, request->offset, request->value);
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pthread_mutex_unlock(&xdev->mtx);
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pthread_mutex_lock(&xdev->async_tmx);
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STAILQ_REMOVE_HEAD(&xdev->async_head, link);
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free(request);
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}
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pthread_mutex_unlock(&xdev->async_tmx);
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return NULL;
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}
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static int
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pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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@ -4548,6 +4642,15 @@ pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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if (error)
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goto done;
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xdev->async_transfer = true;
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pthread_cond_init(&xdev->async_cond, NULL);
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pthread_mutex_init(&xdev->async_tmx, NULL);
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STAILQ_INIT(&xdev->async_head);
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error = pthread_create(&xdev->async_thread, NULL, pci_xhci_ansyc_thread,
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(void *)xdev);
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if (error)
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goto done;
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xhci_in_use = 1;
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done:
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if (error) {
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@ -4603,6 +4706,14 @@ pci_xhci_deinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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pthread_join(xdev->vbdp_thread, NULL);
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sem_close(&xdev->vbdp_sem);
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pthread_mutex_lock(&xdev->async_tmx);
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xdev->async_transfer = false;
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pthread_cond_signal(&xdev->async_cond);
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pthread_mutex_unlock(&xdev->async_tmx);
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pthread_join(xdev->async_thread, NULL);
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pthread_cond_destroy(&xdev->async_cond);
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pthread_mutex_destroy(&xdev->async_tmx);
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pthread_mutex_destroy(&xdev->mtx);
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free(xdev);
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xhci_in_use = 0;
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