hv: disable more features from guest CPUID

Silicon Debug Feature: CPUID.01H.ECX[11]
- We can't allow guests to have direct access to silicon wide resources.

Machine Check Exception: CPUID.01H.EDX[5]
- Need HV support before exposing it to the guests.

Perfmon and Debug: CPUID.01H.ECX[15]
Debug Store: CPUID.01H.EDX[21], CPUID.01H.ECX[2], CPUID.01H.ECX[4]
- HV emulation is needed to separate host and guest monitoring data.
- guest CPUID.0AH is forced to all-zero in ACRN so it makes sense to clear
  these bits as well.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>

hypervisor/include/arch/x86/cpuid.h

@@ -26,6 +26,7 @@
 #define CPUID_ECX_TM2           (1U<<8U)
 #define CPUID_ECX_SSSE3         (1U<<9U)
 #define CPUID_ECX_CID           (1U<<10U)
+#define CPUID_ECX_SDBG          (1U<<11U)
 #define CPUID_ECX_FMA           (1U<<12U)
 #define CPUID_ECX_CX16          (1U<<13U)
 #define CPUID_ECX_ETPRD         (1U<<14U)

hypervisor/include/arch/x86/msr.h

@@ -253,6 +253,7 @@
 #define MSR_IA32_A_PMC5				0x000004C6U
 #define MSR_IA32_A_PMC6				0x000004C7U
 #define MSR_IA32_A_PMC7				0x000004C8U
+#define MSR_IA32_MCG_EXT_CTL			0x000004D0U
 #define MSR_IA32_SGX_SVN_STATUS			0x00000500U
 #define MSR_IA32_RTIT_OUTPUT_BASE		0x00000560U
 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS		0x00000561U